The various arguments for introducing optical interconnections to silicon CMOS chips are summarized, and the challenges for optical, optoelectronic, and integration technologies are discussed. Optics could solve many physical problems of interconnects, including precise clock distribution, system synchronization (allowing larger synchronous zones, both on-chip and between chips), bandwidth and density of long interconnections, and reduction of power dissipation. Optics may relieve a broad range of design problems, such as crosstalk, voltage isolation, wave reflection, impedance matching, and pin inductance. It may allow continued scaling of existing architectures and enable novel highly interconnected or high-bandwidth architectures. No physical breakthrough is required to implement dense optical interconnects to silicon chips, though substantial technological work remains. Cost is a significant barrier to practical introduction, though revolutionary approaches exist that might achieve economies of scale. An Appendix analyzes scaling of on-chip global electrical interconnects, including line inductance and the skin effect, both of which impose significant additional constraints on future interconnects. Keywords—Off-chip wiring, on-chip wiring, optical interconnects, quantum-well modulator, vertical-cavity surface-emitting laser. I.

Abstract — We examine the current performance and future demands of interconnects to and on silicon chips. We compare electrical and optical interconnects and project the requirements for optoelectronic and optical devices if optics is to solve the major problems of interconnects to future high performance silicon chips. Optics has potential benefits in interconnect density, energy and timing. The necessity of low interconnect energy imposes low limits especially on the energy of the optical output devices, with a ~ 10 fJ/bit device energy target emerging. Some optical modulators and radical laser approaches may meet this requirement. Low (e.g., a few fF or less) photodetector capacitance is important. Very compact wavelength splitters are essential for connecting the information to fibers. Dense waveguides are necessary on-chip or on boards for guided wave optical approaches, especially if very high clock rates or dense WDM are to be avoided. Free space optics potentially can handle the necessary bandwidths even without fast clocks or WDM. With such technology, however, optics may enable the continued scaling of interconnect capacity required by future chips. Index Terms—ITRS roadmap, optical interconnections, optical modulators O I.

...................................................................................................................................... viii List of publications .......................................................................................................................ix Chapter 1: Introduction..................................................................................................................1 1.1 Scope and overall research contribution..............................................................................1 1.2 Motivation............................................................................................................................2 1.2.1 The interconnect problem .............................................................................................2 1.2.2 Capabilities and limitations of electrical interconnects................................................4 1.2.3 Advantages of optical interconnects ......................................

ABSTRACT- This paper analyses the performance of different interconnect technologies for on-chip clock distribution, including conventional, three-dimensional (3D), optical, and RF interconnects. Skew, power, and area usage were estimated for each of these technologies based on the 2001 International Technology Roadmap for Semiconductors (ITRS). Our results indicate that most of the skew and power are associated with local clock distribution. Consequently, since the alternative clock distribution approaches that have been proposed focus on global clock distribution, we have not found significant advantages over conventional clock distribution in terms of skew and power. Furthermore, it was found that low skews could be attained with conventional clock distribution schemes if the clock signals are not scaled down. I.

We review some of the relatively fundamental work in the area of optically interconnected digital computing systems. We cover comparisons of optical interconnections with other interconnection media in terms of energy and interconnection density, studies determining the optimal combination of optical and electrical interconnections that should be used, work on free-space optical interconnection architectures, complexity studies, and work on physical and logical system architectures and algorithms. We exclude work on devices, components, materials, and manufacturing. 1.

Computer architects have realized that interconnection bandwidth has become a critical limitation to the development of highperformance multiprocessor systems. Major reason is that the progress of processor performance has increasingly outpaced that of the interconnection networks, thereby limiting the usefulness of multiprocessor systems. This work presents a comprehensive study and the development of optoelectronic-based network routers. Optoelectronic technology can potentially provide ample bandwidth required by multiprocessor systems but at the same time can raise some critical issues that are discussed here such as on-chip wiring and chip packaging. We also proposed new architectural techniques suitable for the development of optoelectronic-based network routers to increase the network bandwidth utilization.

A 1.6Gb/s receiver for optical communication has been designed and fabricated in a 0.25-m CMOS process. This receiver has no transimpedance amplifier and uses the parasitic capacitor of the flip-chip bonded photodetector as an integrating element and resolves the data with a double-sampling technique. A simple feedback loop adjusts a bias current to the average optical signal, which essentially "AC couples" the input. The resulting receiver resolves an 11A input, dissipates 3mW of power, occupies 80m x 50m of area and operates at over 1.6Gb/s.

Processor speeds continue to increase rapidly due to the scaling of CMOS line-widths, but electrical interconnect speeds have not grown at the same rate. The loss mechanisms in electrical interconnects limit their ultimate capacity. Optical interconnects have the potential to alleviate this interconnect bottleneck. At short scales such as board-to-board, chip-to-chip, and on-chip, the important requirements for these optical interconnects are low latency, high throughput, high density, high bandwidth, and simple integration with mainstream silicon technology. This thesis investigates optical interconnects designed to meet these requirements using short pulses, in conjunction with multiple quantum well (MQW) diodes filp-chip bonded to silicon CMOS chips. The use of short optical pulses (100 fs to a few ps), equivalent to a return-to-zero (RZ) format with very low duty cycle, has many potential advantages. We show that using short pulses in optical links can, a) enhance the sensitivity of the receiver

approach to the role of optics

The increased demands of high data-rate communications could be satisfied by optical semiconductor elements. Actually, these devices represent an important role in the total energy budget available for the chip. This work presents a lowpower encoding technique which optimizes the statistical distribution so to reduce the energy dissipated in optical communications. We evaluated the encoding circuits referring to an 180nm, 130 nm and 90 nm CMOS technologies. Our results show an up to 12% electrical current reduction in the on-chip light emitter.