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27
The impact of combined channel mismatch effects in timeinterleaved ADCs
 IEEE Transactions on Instrumentation and Measurement
, 2005
"... converter (ADC) achieves high sampling rates with the drawback of additional distortions caused by channel mismatches. In this paper, we consider the dependency of the signaltonoiseanddistortion ratio (SINAD) on the combination of several different channel mismatch effects. By using either expli ..."
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Cited by 35 (16 self)
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converter (ADC) achieves high sampling rates with the drawback of additional distortions caused by channel mismatches. In this paper, we consider the dependency of the signaltonoiseanddistortion ratio (SINAD) on the combination of several different channel mismatch effects. By using either explicitly given mismatch parameters or given parameter distributions, we derive closedform equations for calculating the explicit or the expected SINAD for an arbitrary number of channels. Furthermore, we extend the explicit SINAD by the impact of timing jitter. We clarify how channel mismatches interact and perform a worst case analysis of the explicit SINAD for individual mismatch errors. We also show that equations describing the expected SINAD of individual mismatch errors are special cases of our general formulation. We indicate how to use the expected SINAD for finding efficient optimization priorities and demonstrate the importance of worst case analyses. Index Terms—Analogtodigital converter (ADC), channel mismatch, error analysis, signaltonoiseanddistortion ratio (SINAD), timeinterleaving, timing jitter.
Adaptive digital correction of analog errors in MASH ADCs. I. Offline and blind online calibration
 IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
, 2000
"... Abstract—Cascaded delta–sigma (MASH) modulators for higher order oversampled analogtodigital conversion rely on precise matching of contributions from different quantizers to cancel lower order quantization noise from intermediate delta–sigma stages. This first part of the paper studies the effect ..."
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Abstract—Cascaded delta–sigma (MASH) modulators for higher order oversampled analogtodigital conversion rely on precise matching of contributions from different quantizers to cancel lower order quantization noise from intermediate delta–sigma stages. This first part of the paper studies the effect of analog imperfections in the implementation, such as finite gain of the amplifiers and capacitor ratio mismatch, and presents algorithms and architectures for digital correction of such analog imperfections, as well as gain and spectral distortion in the signal transfer function. Digital correction is implemented by linear finiteimpulse response (FIR) filters, of which the coefficients are determined through adaptive offline or online calibration. Of particular interest is an online “blind ” calibration technique, that uses no reference and operates directly on the digital output during conversion, with the only requirement on the unknown input signal that its spectrum be bandlimited. Behavioral simulations on dualquantization oversampled converters demonstrate nearperfect adaptive correction and significant improvements in signaltoquantizationnoise performance over the uncalibrated case, using as few as 5 FIR coefficients. An alternative online adaptation technique using test signal injection and experimental results from silicon are presented in the second part, in a companion paper [1]. Index Terms—Adaptation, analogtodigital conversion, blind
Gain and offset mismatch calibration in timeinterleaved multipath A/D sigmadelta modulators
 IEEE Transactions on Circuits and Systems I: Regular Papers
, 2004
"... Abstract—In this paper, we propose a digital background adaptive calibration technique for correcting offset and gain mismatches in timeinterleaved multipath analog–digital (A/D) sigma–delta () modulators. The proposed technique allows us to cancel the spurious tones introduced by offset and gain m ..."
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Cited by 8 (1 self)
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Abstract—In this paper, we propose a digital background adaptive calibration technique for correcting offset and gain mismatches in timeinterleaved multipath analog–digital (A/D) sigma–delta () modulators. The proposed technique allows us to cancel the spurious tones introduced by offset and gain mismatches among the paths only by processing the digital output, without interfering with the operation of the modulator. This solution is also effective for any other timeinterleaved A/D converter topology. Simulation results on a highperformance fourpath bandpass modulator, operating on a 5MHz band at a clock frequency of 320 MHz, demonstrate the effectiveness of the proposed calibration technique, which allows us to achieve significant improvements of the signaltonoise ratio and the spuriousfree dynamic range in the presence of mismatches. Index Terms—Analog–digital conversion, calibration, sigma–delta modulation,path circuits.
Timeinterleaved sigmadelta modulator using output prediction scheme
 IEEE Trans. Circuits and Systems II
, 2004
"... Abstract—A timeinterleaved sigma–delta modulator using the output prediction scheme is proposed. This approach uses only one integrator channel along with incomplete integrator output terms to eliminate the quantizer domino which is a key limit for practical circuit implementation of conventional t ..."
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Cited by 7 (5 self)
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Abstract—A timeinterleaved sigma–delta modulator using the output prediction scheme is proposed. This approach uses only one integrator channel along with incomplete integrator output terms to eliminate the quantizer domino which is a key limit for practical circuit implementation of conventional timeinterleaved sigma–delta modulators. In addition, channel mismatch effects due to mismatch within multiple integrator feedback paths can be reduced by optimizing the feedback path. An equivalent twochannel timeinterleaved version of the conventional secondorder sigma–delta modulator is realized to verify the proposed method. Index Terms—Channel mismatch, incomplete integrator outputs, output prediction, quantizer domino, sigma–delta modulators, timeinterleaved. I.
Domino free 4path timeinterleaved second order sigmadelta modulator
 in Proc. IEEE Int. Symp. Circuits Syst., May 2004
"... A domino free 4path timeinterleaved (TI) second order sigmadelta modulator is proposed. The domino effect, which is a critical limit for the circuit implementation of conventional 4path TI sigmadelta modulators, can be eliminated by the proposed modulator output prediction method. This along wi ..."
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A domino free 4path timeinterleaved (TI) second order sigmadelta modulator is proposed. The domino effect, which is a critical limit for the circuit implementation of conventional 4path TI sigmadelta modulators, can be eliminated by the proposed modulator output prediction method. This along with the input signal down sampling scheme enables a complete SC circuit implementation of the 4path TI modulator with only five opamps, using the conventional 2phase clock control. Also, the single global feedback path of the proposed structure makes it robust to path mismatch effects compared to other TI modulators, which usually have multipath global feedbacks. 1.
Modeling, Identification, and Compensation of Channel Mismatch Errors in TimeInterleaved AnalogtoDigital Converters
, 2005
"... Moderne Signalverarbeitungsanwendungen, wie sie in der Nachrichtentechnik und Messtechnik verwendet werden, benötigen sehr schnelle AnalogDigitalUmsetzer (ADU), was durch eine räumlich parallele Anordnung von zeitlich versetzt arbeitenden ADUs (ADUArray) erreicht werden kann. Die zeitliche Versc ..."
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Cited by 3 (1 self)
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Moderne Signalverarbeitungsanwendungen, wie sie in der Nachrichtentechnik und Messtechnik verwendet werden, benötigen sehr schnelle AnalogDigitalUmsetzer (ADU), was durch eine räumlich parallele Anordnung von zeitlich versetzt arbeitenden ADUs (ADUArray) erreicht werden kann. Die zeitliche Verschiebung ermöglicht, im Vergleich
A PowerEfficient TwoChannel TimeInterleaved ∆∑ Modulator for Broadband Applications
 IEEE Journal of SolidState Circuits
, 2007
"... sigmadelta modulator for broadband applications including asymmetrical digital subscriber line (ADSL) is presented. The proposed twochannel modulator uses a single integrator channel which does not require additional active elements for the quantizer input generation, since the integrator output ..."
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sigmadelta modulator for broadband applications including asymmetrical digital subscriber line (ADSL) is presented. The proposed twochannel modulator uses a single integrator channel which does not require additional active elements for the quantizer input generation, since the integrator outputs are directly used as the input of the quantizers. As a result, the entire modulator can be implemented using only two opamps, which is beneficial for both power consumption and area. Furthermore, this architecture is robust to channel mismatch effects and can operate with a simple clocking scheme. The modulator achieves a dynamic range of 85 dB over a 1.1MHz signal bandwidth with an effective clock frequency of 132 MHz. The circuit is implemented in 0.18 m CMOS technology using metal–insulator–metal capacitors. The total power consumption of the modulator is 5.4 mW from a 1.8V supply and occupies an active area of 1.1 mm2. Index Terms—Channel mismatch, effective clock frequency, sigmadelta () modulator, signal bandwidth, single integrator channel, timeinterleaved (TI). I.
Architecture alternatives for timeinterleaved and inputfeedforward deltasigma modulators
, 2008
"... This thesis provides architecture alternatives for deltasigma modulators in two areas: highspeed operation based on timeinterleaving and lowvoltage environment by exploiting the inputfeedforward concept. Parallelism based on timeinterleaving can be used to increase the speed of deltasigma mod ..."
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This thesis provides architecture alternatives for deltasigma modulators in two areas: highspeed operation based on timeinterleaving and lowvoltage environment by exploiting the inputfeedforward concept. Parallelism based on timeinterleaving can be used to increase the speed of deltasigma modulators. A novel singlepath timeinterleaved architecture is derived and analyzed. Finite opamp gain and bandwidth result in a mismatch between the noise transfer functions of the internal quantizers which degrades the performance of the new modulator. Two techniques are presented to mitigate the mismatch problem: a hybrid topology where the first stage uses multiple integrators while the rest of the modulator uses a single path of integrators and a digital calibration method. The inputfeedforward technique removes the inputsignal component from the internal nodes of deltasigma modulators. The removal of the signal component reduces the signal swing and distortion requirements for the opamps. These characteristics enable the reliable implementation of deltasigma modulators in modern CMOS technology. Two implementation
Design and Simulation of Sigma Delta ADC Using VHDL
 AMS ‖ , International Journal of Engineering Development and Research , Volume 2, Issue 1 ,pp
, 2014
"... Abstract There is two main parts of Sigmadelta ADC: analog modulator and digital filter, the performance of modulator determines the performance of sigmadelta ADC, so the design of modulator is very important. This paper introduces the principle of sigmadelta ADC modulator with high accuracy and ..."
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Abstract There is two main parts of Sigmadelta ADC: analog modulator and digital filter, the performance of modulator determines the performance of sigmadelta ADC, so the design of modulator is very important. This paper introduces the principle of sigmadelta ADC modulator with high accuracy and the applied over sampling technique, noise shaping technique and multibit quantize technique. This paper determines the design scheme of modulator—second orders CIFF (Cascade of integrators, feed forward form) structure and it makes the behavior level verification for this scheme by VHDL AMS. Index Terms — Sigmadelta ADC; modulator; over sampling; noise shaping I.
TimeInterleaved Incremental Data Converters with Low Oversampling Ratios
"... Abstract Incremental ADCs can operate at lower oversampling ratios than ∆Σ modulators, resulting in higher input signal bandwidths. In this paper it is shown that timeinterleaving can further increase the input signal bandwidth in incremental ADCs to the point that the oversampling ratio is equal ..."
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Abstract Incremental ADCs can operate at lower oversampling ratios than ∆Σ modulators, resulting in higher input signal bandwidths. In this paper it is shown that timeinterleaving can further increase the input signal bandwidth in incremental ADCs to the point that the oversampling ratio is equal to the timeinterleaving factor, resulting in no decrease in the allowable input signal bandwidth due to oversampling. This paper investigates some of the advantages and challenges that timeinterleaved incremental ADCs offer, and presents an example where a timeinterleaved by 4 incremental ADC with an oversampling ratio of 4 can attain a resolution of 12 bits. I.