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Methods for True EnergyPerformance Optimization
, 2004
"... This paper presents methods for efficient energyperformance optimization at the circuit and microarchitectural levels. The optimal balance between energy and performance is achieved when the sensitivity of energy to a change in performance is equal for all the design variables. The sensitivitybase ..."
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Cited by 31 (12 self)
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This paper presents methods for efficient energyperformance optimization at the circuit and microarchitectural levels. The optimal balance between energy and performance is achieved when the sensitivity of energy to a change in performance is equal for all the design variables. The sensitivitybased optimizations minimize energy subject to a delay constraint. Energy savings of about 65% can be achieved without delay penalty with equalization of sensitivities to sizing, supply, and threshold voltage in a 64bit adder, compared to the reference design sized for minimum delay. Circuit optimization is effective only in the region of about 30% around the reference delay; outside of this region the optimization becomes too costly either in terms of energy or delay. Using optimal energydelay tradeoffs from the circuit level and introducing more degrees of freedom, the optimization is hierarchically extended to higher abstraction layers. We focus on the microarchitectural optimization and demonstrate that the scope of energyefficient optimization can be extended by the choice of circuit topology or the level of parallelism. In a 64bit ALU example, parallelism of five provides a threefold performance increase, while requiring the same energy as the reference design. Parallel or timemultiplexed solutions significantly affect the area of their respective designs, so the overall design cost is minimized when optimal energyarea tradeoff is achieved.
Noise Considerations in Circuit Optimization
 In Proc. International Conference on ComputerAided Design
, 1998
"... Noise can cause digital circuits to switch incorrectly and thus produce spurious results. Noise can also have adverse power, timing and reliability e ects. Dynamic logic is particularly susceptible to chargesharing and coupling noise. Thus the design and optimization of a circuit should take noise ..."
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Cited by 13 (0 self)
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Noise can cause digital circuits to switch incorrectly and thus produce spurious results. Noise can also have adverse power, timing and reliability e ects. Dynamic logic is particularly susceptible to chargesharing and coupling noise. Thus the design and optimization of a circuit should take noise considerations into account. Such considerations are typically stated as semiin nite constraints. In addition, the number of signals to be checked and the number of subintervals of time during which the checking must be performed can potentially be very large. Thus, the practical incorporation of noise constraints during circuit optimization is a hitherto unsolved problem. This paper describes a novel method for incorporating noise considerations during automatic circuit optimization. Semiin nite constraints representing noise considerations are rst converted toordinary equality constraints involving time integrals, which are readily computed in the context of circuit optimization based on timedomain simulation. Next, the gradients of these integrals are computed by the adjoint method. By using an augmented Lagrangian optimization merit function, the adjoint method is applied tocompute all the necessary gradients required for optimization in a single adjoint analysis, no matter how many noise measurements are considered and irrespective of the dimensionality of the problem. Numerical results are presented. 1
TwoStep Algorithms for Nonlinear Optimization with Structured Applications
 SIAM Journal on Optimization
, 1999
"... In this paper we propose extensions to trustregion algorithms in which the classical step is augmented with a second step that we insist yields a decrease in the value of the objective function. The classical convergence theory for trustregion algorithms is adapted to this class of twostep alg ..."
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Cited by 10 (6 self)
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In this paper we propose extensions to trustregion algorithms in which the classical step is augmented with a second step that we insist yields a decrease in the value of the objective function. The classical convergence theory for trustregion algorithms is adapted to this class of twostep algorithms. The algorithms can be applied to any problem with variable(s) whose contribution to the objective function is a known functional form. In the nonlinear programming package LANCELOT, they have been applied to update slack variables and variables introduced to solve minimax problems, leading to enhanced optimization eciency. Extensive numerical results are presented to show the eectiveness of these techniques. Keywords. Trust regions, line searches, twostep algorithms, spacer steps, slack variables, LANCELOT, minimax problems, expensive function evaluations, circuit optimization. AMS subject classications. 49M37, 90C06, 90C30 1 Introduction In nonlinear optimization proble...
An Efficient Technique for Device and Interconnect Optimization in Deep Submicron Designs
 in Proc. Int. Symp. on Physical Design
, 1997
"... In this paper, we formulated a new class of optimization problem, named the general CHposynomial program, which is more general than the simple and boundedvariation CHposynomial programs in [1]. We revealed the general dominance property so that an efficient and unified algorithm based on the loc ..."
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Cited by 7 (2 self)
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In this paper, we formulated a new class of optimization problem, named the general CHposynomial program, which is more general than the simple and boundedvariation CHposynomial programs in [1]. We revealed the general dominance property so that an efficient and unified algorithm based on the local refinement (LR) operation can be used to optimize the simple, boundedvariation and general CHposynomial programs. We applied the LRbased optimization algorithm to solve the device sizing problem using accurate tablebased model, and the wire sizing and spacing problem with consideration of coupling between multiple nets. Both problems are solved in the context of simultaneous device and wire sizing optimization for deep submicron designs. Experiments show that our LRbased optimization algorithm is very effective and extremely efficient. Up to 16.5% delay reduction is observed when compared with previous work based on the simple device model [1], and up to 31% delay reduction and 100x speedup is observed when compared the global interconnect sizing and spacing work [2]. We believe that our general CHposynomial formulation and LRbased algorithm can also be applied to other optimization problems in the CAD field.
Circuit Optimization via Adjoint Lagrangians
 IEEE INTERNATIONAL CONFERENCE ON COMPUTERAIDED DESIGN
, 1997
"... The circuit tuning problem is best approached by means of gradientbased nonlinear optimization algorithms. For large circuits, gradient computation can be the bottleneck in the optimization procedure. Traditionally, when the number of measurements is large relative to the number of tunable paramete ..."
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Cited by 6 (3 self)
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The circuit tuning problem is best approached by means of gradientbased nonlinear optimization algorithms. For large circuits, gradient computation can be the bottleneck in the optimization procedure. Traditionally, when the number of measurements is large relative to the number of tunable parameters, the direct method [2] is used to repeatedly solve the associated sensitivity circuit to obtain all the necessary gradients. Likewise, when the parameters outnumber the measurements, the adjoint method [1] is employed to solve the adjoint circuit repeatedly for each measurement to compute the sensitivities. In this paper, we propose the adjoint Lagrangian method, which computes all the gradients necessary for augmentedLagrangianbased optimization in a single adjoint analysis. After the nominal simulation of the circuit has been carried out, the gradients of the merit function are expressed as the gradients of a weighted sum of circuit measurements. The weights are dependent on the nominal solution and on optimizer quantities such as Lagrange multipliers. By suitably choosing the excitations of the adjoint circuit, the gradients of the merit function are computed via a single adjoint analysis, irrespective of the number of measurements and the number of parameters of the optimization. This procedure requires close integration between the nonlinear optimization software and the circuit simulation program. The adjoint
Optimisation of FullCustom Logic Cells Using Response Surface Methodology
, 2000
"... Introduction: The design of digital circuits, especially for fullcustom cells, is often a time consuming and laborious process relying on the intuition and heuristic knowledge of the designer. Optimising transistor sizes is the main key in meeting the various design specifications such as timedela ..."
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Introduction: The design of digital circuits, especially for fullcustom cells, is often a time consuming and laborious process relying on the intuition and heuristic knowledge of the designer. Optimising transistor sizes is the main key in meeting the various design specifications such as timedelay, area and power. The problem with this type of design optimisation is the large number of design variables leading to an explosion in the design space. Various solutions to these problems have been proposed which are based on the use of either static timing models [1], dynamic timing models [2] or a combination of the two [3]. Static timing models, while efficient in computation, do not take all transition states into account, resulting in low accuracy. Dynamic timing models, on the other hand, require the consideration of all possible input combinations and therefore suffer from the dimensionality problem. We propose to use a set of techniques known as design of experiments (DOE)
Noise Considerations in . . .
"... Noise can cause digital circuits to switch incorrectly, producing spurious results. It can also have adverse power, timing and reliability effects. Dynamic logic is particularly susceptible to chargesharing and coupling noise. Thus the design and optimization of a circuit should take noise consider ..."
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Noise can cause digital circuits to switch incorrectly, producing spurious results. It can also have adverse power, timing and reliability effects. Dynamic logic is particularly susceptible to chargesharing and coupling noise. Thus the design and optimization of a circuit should take noise considerations into account. Such considerations are typically stated as semiinfinite constraints in the timedomain. Semiinfinite problems are generally harder to solve than standard nonlinear optimization problems. Moreover, the number of noise constraints can potentially be very large. This paper
Michael OrshanskyStatistical Characterization For Timing SignOff: From Silicon to
"... My inexpressible gratitude goes to my advisor Prof. Jacob Abraham for not just the best advisor I could have desired, but also the visionary and enthusiastic researcher that has impacted me in several ways. I would also like to thank him for the research freedom and support that have made my PhD an ..."
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My inexpressible gratitude goes to my advisor Prof. Jacob Abraham for not just the best advisor I could have desired, but also the visionary and enthusiastic researcher that has impacted me in several ways. I would also like to thank him for the research freedom and support that have made my PhD an enjoyable and smooth experience. I would like to thank my mentor, Prof. David Blaauw, at the University of Michigan, who played an instrumental role in providing me with guidance and expertise during this research. My working experience with him at Motorola has been one of the most rewarding experiences and has enabled me to stay focused on being current with the technology. I am thankful to my dissertation committee members, Prof. David Pan, Prof. Robert Flake and Prof. Michael Orshansky for taking the time out of their schedules to review my research and provide useful feedback. All the research for this Ph.D. was done while working at Freescale Semiconductor. I would like to thank several coauthors and collaborators for their cooperation and providing timely feedbacks which was instrumental in making this research happen. Especially, I would like to thank Dr. Rajendran Panda for providing me with an enjoyable work environment at Freescale Semiconductor. I am thankful to Alexandre Ardelea, Robert Maziasz, Yun Zhang, Lucie Nechanicka,