The new generation of silicon retinae has two defining characteristics. First, these synthetic retinae are morphologically equivalent to their biological counterparts---at an appropriate level of abstraction. Second, they accomplish all four major operations performed by biological retinae using neurobiological principles: (1) continuous sensing for detection, (2) local automatic gain control for amplification, (3) spatiotemporal bandpass filtering for preprocessing, and (4) adaptive sampling for quantization. I introduce the term retinomorphic to refer to this subclass of the neuromorphic electronic systems [30]. I compare and contrast their design principles with the standard practice in imager design. I argue that neurobiological principles are best suited to perceptive systems [43] that go beyond reproducing the dynamic scene, like a conventional video camera does, to extracting salient information in real time [3]. I shall present results from a fully operational retinomorphic vis...

Abstract—We present a transmitter for a scalable multiple-access inter-chip link that communicates binary activity between two-dimensional arrays fabricated in deep submicrometer CMOS. Transmission is initiated by active cells but cells are not read individually. An entire row is read in parallel; this increases communication capacity with integration density. Access is random but not inequitable. A row is not reread until all those waiting are serviced; this increases parallelism as more of its cells become active in the mean time. Row and column addresses identify active cells but they are not transmitted simultaneously. The row address is followed sequentially by a column address for each active cell; this cuts pad count in half without sacrificing capacity. We synthesized an asynchronous implementation by performing a series of program decompositions, starting from a high-level description. Links using this design have been implemented successfully in

Analysis of dynamic-range (DR) and signal-to-noise-ratio (SNR) for high fidelity, high-dynamic-range (HDR) image sensor architectures is presented. Four architectures are considered: (i) time-to-saturation, (ii) multiplecapture, (iii) asynchronous self-reset with multiple capture, and (iv) synchronous self-reset with residue readout. The analysis takes into account circuit nonidealities such as quantization noise and the effects of limited pixel area on building block and reference signal performance and accuracy. Examples that demonstrate the behavior of SNR in the extended DR and implementation and power consumption issues for each scheme are presented.

A set of test structures designed to characterize and compare the performance of CMOS passive and active pixel image sensors is presented. The test structures are designed so that they can be rapidly ported from one process to another. They are also designed so that individual photodetectors and pixel circuits as well as entire image sensor arrays can be characterized and compared based on: quantum e#ciency, spectral response, #xed pattern noise, sensitivity, blooming, input referred read noise, reduction of quantum e#ciency caused by silicide#salicide, lag, digital switching noise sensitivity, impact ionization noise sensitivity, dynamic range, and temperature dependency of all measured parameters. Four test chips that include a variety of these structures have been built in two di#erent 0.35#m CMOS processes. The test chips include nineteen types of individual photodetectors and thirty eighttypes of 64#64 pixel arrays. The test methodology and preliminary test results from these chip...

this paper, we argue that biological vision and electronic image acquisition share common principles despite their vastly different implementations. These shared principles are based on the need to acquire a common set of input stimuli as well as the need to generalize from the acquired images. Two related principles are discussed in detail, namely, multiple parallel image representations and the use of dedicated local memory in various stages of acquisition and processing. We review relevant literature in visual neuroscience and image systems engineering to support our argument. Particularly, the paper discusses multiple capture image acquisition, with applications such as dynamic range, field-of-view, or depth-of-field extension. Finally, as an example, a novel multiplecapture -single-image complementary metal--oxide--semiconductor sensor is presented. This sensor has been developed at Stanford University and it illustrates the principles that are shared among biological vision and image acquisition

A micro-spectrometer has been realized based on an array of Fabry-Perot thin-film optical resonators. The 16 channel micro-spectrometer is IC fabrication compatible and operates in the visible spectral range with an inter-channel shift of 6 nm. Each of the channels is sensitive in a single peak with FWHM of 16 nm. A FWHM < 2 nm and finesse of 40 for narrowband operation is demonstrated. Introduction Numerous applications, e.g. systems for chemical analysis by optical absorption and emission line characterization, will benefit from the availability of low-cost single-chip spectrometers. Miniaturized spectrometers will offer significant advantages over existing instruments, including size reduction, low cost, fast data-acquisition and high reliability. Previously developed micro-spectrometers [1-5], fabricated using bulk or surface micromachining, contain movable parts to perform wavelength tuning. As a result, these are less reliable and suitable only for operation in a limited spectr...

Two techniques for performing pixel level analog to digital conversion (ADC) are reviewed. The first is an oversampling technique which uses a one bit first order Ez modulator for each 2 x 2 block of pixels to directly convert photocharge to bits. Each modulator is implemented using 17 transistors. The second technique is a Nyquist rate multi—channel--bit—serial (MCBS) ADC. The technique uses successive comparisons to convert the pixel voltage to bits. Results obtained from implementations of these ADC techniques are presented. The techniques are compared based on size, charge handling capacity, FPN, noise sensitivity, data throughput, quantization, memory/processing, and power dissipation requirements for both visible and JR imagers. From the comparison it appears that the L\ ADC is better suited to JR imagers, while the MCBS ADC is better suited to imagers in the visible range.

converter (ADC) is presented. The ADC is ideally suited to pixel-level implementation in a CMOS image sensor. The ADC uses successive comparisons to output one bit at a time simultaneously from all pixels. It is implemented using a 1-bit comparator/latch pair per pixel or per group of neighboring pixels, and a digital-to-analog-converter/controller shared by all pixels. The comparator/latch pair operates at very slow speeds and can be implemented using simple robust circuits. The ADC’s can be fully tested by applying electrical signals without any optics or light sources. A CMOS 320 2 256 sensor using the MCBS ADC is described. The chip measures 4.14 2 5.16 mm 2. It achieves 10 2 10 m 2 pixel size at 28 % fill factor in 0.35m CMOS technology. Each 2 2 2 pixel block shares an ADC. The pixel block circuit comprises 18 transistors. It operates in subthreshold to maximize gain and minimize power consumption. The power consumed by the sensor array is 20 mW at 30 frames/s. The measured integral nonlinearity is 2.3 LSB, and differential nonlinearity is 1.2 LSB at eight bits of resolution. The standard deviation of the gain and offset fixed pattern noise due to the ADC are 0.24 and 0.2%, respectively. Index Terms — Analog-to-digital conversion, cameras, CMOS image sensors, image sensors, mixed analog–digital integrated circuits, pixel-level analog-to-digital converter (ADC), video cameras. I.

The technology to build highly integrated 3-dimensional computational image sensors by stacking and interconnecting layers of 2-dimensional silicon ICs is being developed. Unlike multi-chip module (MCM-V) packaging, in which interconnect lines are brought to the periphery of a chip stack to achieve vertical integration, this new technology allows virtually unrestricted placement of vertical vias within the interior of the chip. The goal of this development is to enable high speed, high resolution image processing in compact low power wearable systems that would be coupled with a head-mounted display (HMD). Potential applications for these systems include target tracking and image stabilization. In this talk we focus on the architecture of the 3D image sensor, which includes pixel-parallel analog-to-digital conversion and programmable digital processors for pixel and block operations. We show that 3D technology will allow at least an order of magnitude decrease in power dissipation over...

The paper investigates the suitability of Σ ∆ modulation based FPA readout schemes for use in Vertically Interconnected Sensor Arrays requiring ultra high dynamic range and frame rate. It is shown that the extended counting scheme is capable of achieving the DR and frame rate requirements but at the expense of high power consumption. Extended counting is also shown to outperform several other HDR schemes in terms of SNR at the ultra high DR and frame rate.