As the IC devices is scaled into nanometer dimen- sions and operates in giga-hertz frequencies, interconnect design and optimization have become critical in determining the system performance and reliability.

This paper presents an efficient approach to perform global interconnect sizing and spacing (GISS) for multiple nets to minimize interconnect delays with consideration of coupling capacitance, in addition to area and fringing capacitances. We introduce the formulation of symmetric and asymmetric wire sizing and spacing. We prove two important results on the symmetric and asymmetric effective-fringing properties which leadtoavery effective bound computation algorithm to compute the upper and lower bounds of the optimal wire sizing and spacing solution for all nets under consideration. Our experiments show that in most cases the upper and lower bounds meet quickly after a few iterations and we actually obtain the optimal solution. To our knowledge, this is the first in-depth study of global wire sizing and spacing for multiple nets with consideration of coupling capacitance. Experimental results show that our GISS solutions lead to substantial delay reduction than existing single net wire-sizing solutions without consideration of coupling capacitance.

In this paper, we study the performance driven multiway circuit partitioning problem with consideration of the significant difference of local and global interconnect delay induced by the partitioning. We develop an efficient algorithm HPM (Hierarchical Performance driven Multi-level partitioning) that simultaneously considers cutsize and delay minimization with retiming. HPM builds a multi-level cluster hierarchy and performs various refinement while gradually decomposing the clusters for simultaneous cutsize and delay minimization. We provide comprehensive experimental justification for each step involved in HPM and in-depth analysis of cutsize and delay tradeoff existing in the performance driven partitioning problem. HPM obtains (i) 7% to 23% better delay compared to the state-of-the-art cutsize driven hMetis [11] at the expense of 19% increase in cutsize, and (ii) 81% better cutsize compared to the state-of-the-art delay driven PRIME [2] at the expense of 6% increase in delay.

This paper presents a set of interconnect performance estimation models for design planning with consideration of various effective interconnect layout optimization techniques, including optimal wire sizing, simultaneous driver and wire sizing, and simultaneous buffer insertion/sizing and wire sizing. These models are extremely efficient, yet provide high degree of accuracy. They have been tested on a wide range of parameters and shown to have over 90% accuracy on average compared to running best-available interconnect layout optimization algorithms directly. As a result, these fast yet accurate models can be used efficiently during high-level design space exploration, interconnect-driven design planning/synthesis, and timing-driven placement to ensure design convergence for deep submicrometer designs.

Abstract- Although the emerging three-dimensional integration technology can significantly reduce interconnect delay, chip area, and power dissipation in nanometer technologies, its impact on overall system performance is still poorly understood due to the lack of tools and systematic flows to evaluate 3D microarchitectural designs. The contribution of this paper is the development of MEVA-3D, an automated physical design and architecture performance estimation flow for 3D architectural evaluation which includes 3D floorplanning, routing, interconnect pipelining and automated thermal via insertion, and associated die size, performance, and thermal modeling capabilities. We apply this flow to a simple, out-of-order superscalar microprocessor to evaluate the performance and thermal behavior in 2D and 3D designs, and demonstrate the value of MEVA-3D in providing quantitative evaluation results to guide 3D architecture designs. In particular, we show that it is feasible to manage thermal challenges with a combination of thermal vias and double-sided heat sinks, and report modest system performance gains in 3D designs for these simple test examples. 1.

-49152 0 157 158 159 7 "! -49152 0 157 158 159 7 9999 9999 -49152 0 157 158 159 7 9999 9999 9999 $67#' 0 157 158 159 7 9999 9999 9999 /! 67#' 0 157 158 159 7 9999 9999 9999 )#$(9/@!2L/@ )%Q/%&/@ #*/ $7U;V!7WX %&/@ )R? #, $7U;V!7WX %&/@ )R?/ ?! ?% 28990-43070 >;,6Z; '= )R?/ )/M/! -43070 >;,6Z; '= )R?/ P>? )L >;,6Z; '= )R?/ Z /@! )L >;,6Z; '= )R?/ =)(\*., 7; ZS4/8V=7#/)?`@,O / ;72/S?.B?;a.`S6 V=7#/)?`@,O / ?/@7*1 /@b7,"=7#/)?.`@;*@Y;L7 *7-#ZS#DJTcM!2TX !7#$K7/4M7;K! ?.`@;*@Y;L7 *7-#ZS#DJTcM!2TX ,2. #,\/! 34700 1(21f?;6 > 00 ?.`@;*@Y;L7 *7...

This paper presents an interconnect-driven floorplanning (IDFP) flow and algorithm integrated with multi-layer global wiring planning (GWP). It considers a number of interconnect performance optimizations during floorplanning, including interconnect topology optimization, layer assignment, buffer insertion, wire sizing and spacing. It also includes fast routability estimation and performance-driven routing for congestion control. Our experiments on the SUN picoJava-II TM core test circuit show that over 74% delay reduction can be achieved using our interconnect-driven floorplanner, compared to a conventional floorplanner without consideration of interconnect performance optimization/planning. We expect that IDFP with GWP will play a central role in designing interconnect-limiting, high-performance integrated circuits. 1 Introduction Global interconnect is commonly recognized as a key factor for designing high-performance integrated circuits, as VLSI process technology migrates into...

In this paper, we describe optimization techniques to minimize important design objectives such as delay, peak noise, delay uncertainty due to noise, power, and cost. In doing so, we employ a new system-performance simulation engine, GTX (GSRC Technology Extrapolation). We concentrate on using accurate models of both circuit and design technology. For example, we take such effects as inductance, repeater staggering, signal line shielding, via parasitics, dynamic delay, and buffer placement uncertainty into account. We examine a typical critical path and apply these optimization techniques using the latest analytical models to determine their potential impact. Results indicate that optimal repeater sizes are significantly smaller than conventional models would suggest, especially when considering energy-delay issues. Also, we demonstrate that optimal wire sizing models need to consider inductive effects and use of the true worst-case capacitive noise switch factor leads to a substantial...

As chip multiprocessors scale to a greater number of processing cores, on-chip interconnection networks will experience dramatic increases in both bandwidth demand and power dissipation. Fortunately, promising gains can be realized via integration of Radio Frequency Interconnect (RF-I) through on-chip transmission lines with traditional interconnects implemented with RC wires. While prior work has considered the latency advantage of RF-I, we demonstrate three further advantages of RF-I: (1) RF-I bandwidth can be flexibly allocated to provide an adaptive NoC, (2) RF-I can enable a dramatic power and area reduction by simplification of NoC topology, and (3) RF-I provides natural and efficient support for multicast. In this paper, we propose a novel interconnect design, exploiting dynamic RF-I bandwidth allocation to realize a reconfigurable network-on-chip architecture. We find that our adaptive RF-I architecture on top of a mesh with 4B links can even outperform the baseline with 16B mesh links by about 1%, and reduces NoC power by approximately 65 % including the overhead incurred for supporting RF-I. 1.

In this paper, we study wire width planning for interconnect performance optimization in an interconnect-centric design flow. We first propose some simplified, yet near-optimal wire sizing schemes, using only one or two discrete wire widths. Our sensitivity study on wire sizing optimization further suggests that there exists a small set of "globally" optimal wire widths for a range of interconnects. We develop general and efficient methods for computing such a "globally" optimal wire width design and show rather surprisingly that using only two "predesigned" widths for each metal layer, we are still able to achieve close to optimal performance compared with that by using many possible widths, not only for one fixed length, but also for all wire lengths assigned at each metal layer. Our wire width planning can consider different design objectives and wire length distributions. Moreover, our method has a predictable small amount of errors compared with optimal solutions. We expect that our simplified wire sizing schemes and wire width planning methodology will be very useful for better design convergence and simpler routing architectures.