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A New Transitive Closure Algorithm with Applications to Redundancy Identification
 in Proc. of the 1st International Workshop on Electronic, Design and Test Applications (DELTA’02
, 2002
"... ..."
A FaultIndependent Transitive Closure Algorithm for Redundancy Identification
 IN PROC. OF THE 16 TH INTERNATIONAL CONF. VLSI DESIGN
, 2003
"... We present a faultindependent redundancy identification algorithm. The controllabilities and observabilities are defined as Boolean variables and represented on an implication graph. A major enhancement over previously published results is that we include all direct and partial implications, as we ..."
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Cited by 8 (5 self)
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We present a faultindependent redundancy identification algorithm. The controllabilities and observabilities are defined as Boolean variables and represented on an implication graph. A major enhancement over previously published results is that we include all direct and partial implications, as well as node fixation. The transitive closure, whose computation now requires a new algorithm, provides many redundant faults in a singlepass analysis. Because of these improvements, we obtain better performance than all previous faultindependent methods at execution speeds that are much faster than any exhaustive ATPG. For example, in the s9234 circuit more than half of the redundant faults are found in just 14 seconds on a Sparc 5. All 34 redundant faults of c6288 are found in one pass. Besides, our single pass procedure can classify faults according to the causes of their redundancy. The weakness of our method, as we illustrate by examples, lies in the lack of a formulation for the observabilities of fanout stems.
Using Contrapositive Law in an Implication Graph to Identify Logic Redundancies
 Proc. 18 th International Conf. VLSI Design
, 2005
"... Abstract – Implication graphs are used to solve the test generation, redundancy identification, synthesis, and verification problems of digital circuits. We propose a new “oring ” node structure to represent partial implications in a graph. The oring node is the contrapositive of the previously used ..."
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Cited by 3 (1 self)
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Abstract – Implication graphs are used to solve the test generation, redundancy identification, synthesis, and verification problems of digital circuits. We propose a new “oring ” node structure to represent partial implications in a graph. The oring node is the contrapositive of the previously used “anding ” node. An ninput gate requires one oring and one anding nodes to represent all partial implications. This implication graph is shown to be more complete and more compact compared to the previously published (n+1) anding node graph. Introduction of the new oring node finds more redundancies using the transitive closure method. The second contribution of the present work is a set of new algorithms to update transitive closure for every newly added edge in the implication
Using Contrapositives to Enhance the Implication Graph of Logic Circuits
 in Proc. of the 13 th IEEE North Atalantic Test Workshop
, 2004
"... Abstract – Implication graphs are used to solve the test generation, redundancy identification, synthesis, and verification problems of digital circuits. We propose a new “oring ” node structure to represent partial implications in a graph. The oring node is the contrapositive of the previously used ..."
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Cited by 1 (1 self)
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Abstract – Implication graphs are used to solve the test generation, redundancy identification, synthesis, and verification problems of digital circuits. We propose a new “oring ” node structure to represent partial implications in a graph. The oring node is the contrapositive of the previously used “anding ” node. The addition of a single oring node in the implication graph of a Boolean gate eliminates the need for several anding nodes. An ninput gate requires one oring and one anding nodes to represent all partial implications. This implication graph is shown to be more complete and more compact compared to the previously published (n+1) anding nodes graph. Introduction of the new oring node finds more redundancies using the transitive closure method. The second contribution of the present work is new algorithms
Theorems on Redundancy Identification
 in Proc. of the 12th North Atlantic Test Workshop
, 2003
"... Redundant logic in a digital circuit is often identified as untestable or redundant single stuckat faults. Redundant faults in a combinational circuit are faults that no input patterns can detect [2]. Removal of such faults simplifies the circuit without chang\Lambda Student ..."
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Cited by 1 (0 self)
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Redundant logic in a digital circuit is often identified as untestable or redundant single stuckat faults. Redundant faults in a combinational circuit are faults that no input patterns can detect [2]. Removal of such faults simplifies the circuit without chang\Lambda Student
Diagnostic Test Pattern Generation . . .
, 2012
"... In VLSI testing we need Automatic Test Pattern Generator (ATPG) to get input test vectors for Circuit Under Test (CUT). Generated test sets are usually compacted to save test time which is not good for failure diagnosis. Physical defects in circuits are modeled by different Fault Models to facilitat ..."
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In VLSI testing we need Automatic Test Pattern Generator (ATPG) to get input test vectors for Circuit Under Test (CUT). Generated test sets are usually compacted to save test time which is not good for failure diagnosis. Physical defects in circuits are modeled by different Fault Models to facilitate test generation. Stuckat and transition fault models are widely used because of their practicality. In this work a Diagnostic Automatic Test Pattern Generation (DATPG) system is constructed by adding new algorithmic capabilities to conventional ATPG and fault simulation programs. The DATPG aims to generate tests to distinguish stuckat fault pairs, i.e., two faults must have different output responses. This will help diagnosis to pin point the failure by narrowing down the fault candidates which may be the reason for this particular failure. Given a fault pair, by modifying circuit netlist a new single fault is modeled. Then we use a conventional ATPG to target that fault. If a test is generated, it is guaranteed to distinguish the fault pair in the original circuit. A fast diagnostic fault simulation algorithm is implemented to find undistinguished fault pairs from a fault list for a given test vector set. To determine the quality of the test vector set