This paper prov6xx an ov ervG8 ofalgorithmic noise-toleranc (ANT) for designing reliable and energy-e#cient digital signal processing systems. Techniques such as prediction-based, error cancellation-based, and reduced precision redundancy based ANT are discussed.Av erage energy-saverg range from 67% to 71% ov er conv entional systems. Fluid IP core generators are proposed as a means of encapsulating the benefits of an ANT-based low-power design methodology. CAD issues resident in such a methodology are also discussed.

Dynamic logic requires some sort of keeper to prevent the output node from floating and to provide acceptable noise immunity. A number of recent papers have advocated using a very weak complementary pMOS network in place of the conventional feedback keeper; such a technique is called Noise-Tolerant Precharge (NTP). This paper compares the delay and noise margin of NTP with conventional feedback keepers. Although NTP is more robust in that it can recover from a dynamic noise event, it is also 5-50% slower than conventional feedback keepers with the same static noise margin.

this paper we present a new noise-tolerant dynamic circuit technique suitable for pipelined dynamic digital circuits. The effectiveness of this technique is demonstrated by means of HSPICE simulations for two kind of gates, CMOS AND and OR gates, both TSPC and Domino. In order to have a clear idea about this proposal's noise immunity improvement we compare its performance with previous works. Simulation results show that the proposed technique has an improvement in the noise tolerance and the 9999 quotient over the conventional dynamic logic and the previous noise-tolerant dynamic circuit techniques with a slight delay and power increase

Dynamic logic can provide significant performance and power benefit compared to implementations using static gates. Unfortunately dynamic gates have traditionally suffered from low noise margins, which limits their reliability. A new logic family, called complementary dynamic logic (CDL), is presented. CDL replaces the standard keeper logic with a dual dynamic keeper gate that is applicable to all dynamic gate structures. CDL provides dynamic gates with two novel characteristics: hysteresis and arbitrarily configurable noise margins. However, these two benefits come at the cost of reducing the gain and increasing the energy of the dynamic gate. This paper compares the noise, energy, performance, gain, and total transistor width tradeoffs of CDL and three other logic families applied to a 65nm cell library consisting of 23 functions. The results show that the performance advantages of dynamic domino gates can be maintained while providing significantly enhanced noise margins using CDL structures. 1.