Abstract—We propose a technique to use dual supply voltages in digital designs to reduce energy consumption. New algorithms are proposed for finding and assigning a lower voltage in a dual voltage design. Given a circuit and a supply voltage and an upper bound on the critical path delay, the first algorithm finds an optimal lower supply voltage and a second algorithm assigns that lower voltage to selected gates. A linear time algorithm described in the literature is used for computing slacks for all gates of the circuit for a given supply voltage. For the computed gate slacks and the lower supply voltage, all gates are divided into three groups such that no gate in the first group can be assigned the lower supply, all gates in the second group can be simultaneously set to lower supply while maintaining positive slack for every gate, and gates in the third group are assigned low voltage, iteratively, in selected subsets at a time. The gate slacks are recalculated after each such voltage assignment. Thus, the overall complexity of this reduced power dual voltage assignment procedure is O(n 2). SPICE simulations of ISCAS’85 benchmark circuits using the 90-nm bulk CMOS technology results show up to 60 % energy savings. Index Terms: Dual-voltage design, Clustered Voltage Scaling (CV S), gate slack, critical path, level converter,

Abstract-The performance of a processor generally means how fast it can execute a task. For a given architecture we can measure the size of a task as the number of clock cycles it will take to execute. Then clock frequency (f ) will determine the execution time. Normally, the frequency can be raised if the supply voltage Vdd is increased. This, however, increases the power and energy used. We introduce a new measure, cycle efficiency (η) as cycles per joule that gives the rate of computational work per unit energy. Similar to f , η is also a function of Vdd. We provide a method of characterizing a processor in terms of its f and η versus Vdd characteristics. Intel Pentium M processor with an assumed 90nm CMOS PTM (predictive technology model) is used as an example. For a demonstration of performance and energy management, we consider a program that executes in 1.8 billion clock cycles. At the nominal operating supply of 1.2V we have f = 1.8GHz and η = 15 megacycles/joule. The program executes in 1 second and uses 120 joules. For operation at 0.6V, f = 277MHz and η = 70 megacycles/joule, resulting in a run time of 6.5 seconds and consumption of 25 joules. We also find a subthreshold voltage extreme of 200mV, f = 54.5MHz and η = 660 megacycles/joule. Now the program will take 33 seconds but will consume only 2.27 joules. Thus, using cycle efficiency and clock frequency one can manage the time and energy performances according to the requirements of a computing task.

Abstract — Evolving nanometer CMOS technologies provide low power, high performance and higher levels of integration but suffer from increased subthreshold leakage and excessive process variation. The present work examines the 45nm bulk and high-k technologies. We evaluate the performance of a 32-bit ripplecarry adder circuit for the entire range of supply voltages over which it displays correct function. Lowering voltage increases delay, reducing the maximum clock cycle rate. We use the maximum permissible clock rate and the energy per cycle at that clock rate as two performance criteria. The minimum energy per cycle operation occurs at a subthreshold voltage. For minimum energy, the bulk technology has a very low performance (~7 MHz). However, high-k technology works at a much higher 250 MHz clock. Faster clock rate reduces the leakage energy making high-k almost twice as energy efficient compared to bulk. The energy per cycle versus supply voltage is a U-shaped curve whose bottom, the minimum energy point, provides a stable equilibrium against speed and energy deviations due to process related parametric variations for different technologies. These deviations can be expected to be lower for high k technology compared to those circuits designed in bulk technology that are commonly in use. These deviations are also lower compared to those at higher supply voltages that are commonly in use. Although we expect the clock rate to further improve and energy per cycle to reduce for 32 nm and finer technologies, some projections indicate that energy per cycle could increase with a move towards finer technologies. However, those studies were conducted on bulk technologies and further investigation should ascertain the performance of the high-k technology. Keywords – Low-power circuits, subthreshold voltage operation, nanometer CMOS devices, high-k CMOS technology, process variation.

This paper investigates subthreshold voltage operation of digital circuits. Starting from the previously known single supply voltage for minimum energy per cycle, we further lower the energy consumption by using dual subthreshold supplies. Level converters, commonly used in the above threshold design, are found to be unacceptably slow for subthreshold voltage operation. Therefore, special constraints are used to eliminate level converters. We give a new mixed integer linear program (MILP) that automatically and optimally assigns gate voltages, avoids the use of level converters, and holds the minimum critical path delay, while minimizing the total energy per cycle. Using examples of a 16-bit ripple-carry adder and a 4 × 4 multiplier we show energy savings of 23 % and 5%, respectively. The latter is a worst case example because most paths are critical. Alternatively, for the same energy as that of single below-threshold supply, an optimized dual voltage design can operate at 3 to 4 times higher clock rate. Also, we show energy saving up to 22.2 % from the minimum energy point over ISCAS’85 benchmark circuits. The MILP optimization with special consideration for level converters is general and applicable to any supply voltage range.

We propose a method for dual supply voltage digital design to reduce energy consumption without violating the given performance requirement. Although the basic idea of placing low voltage gates on non-critical paths is well known, a new two-step procedures does it so more efficiently. First, given a circuit and its nominal single supply voltage, we find a suitable value for a lower second supply voltage that is likely to give the best advantage in power reduction. Besides, using the critical path timing constraint and a linear-time gate slack calculation we also classify gates into three groups. All gates in Group 1 can be simultaneously assigned the lower voltage. Any gate in Group 2 can be assigned the lower voltage but then gate slacks must be recalculated because the group classifications may change. No gate in Group 3 can be assigned the lower voltage. A second step then assigns the lower voltage to the largest possible number of gates using the gate classifications and imposing a topological constraint, preventing any low voltage gate from feeding into a higher voltage gate, thus avoiding the use of level converters. SPICE simulation of dual-voltage ISCAS’85 benchmark circuits using the 90nm bulk CMOS PTM (predictive technology model) shows energy savings of up to 60 % with no increase in the original critical path delay and up to 70 % with relaxed critical path delay.

Abstract—This paper presents a new slack-time based algorithm for dual Vdd design to achieve maximum energy saving. Although a global optimum is sought computation time is kept low. The slack of a gate is defined as the difference between the critical path delay for the circuit and the delay of the longest path through that gate. A linear-time algorithm is used for computing slacks for all gates of the circuit. Positive non-zero slack gates are classified into two groups, one in which all gates can be unconditionally assigned low voltage and the other where only a selected subset can be assigned low voltage without violating the positive non-zero slack requirement. Multiple voltage boundaries are given special consideration. The overall complexity of this power optimization algorithm is linear in number of gates as compared to a previously published exponential-time exact algorithm using mixed integer linear program (MILP). We apply the new algorithm to optimize ISCAS’85 benchmark circuits and compare the results with those from MILP. We avoid the use of level converters at multiple voltage boundaries. Energy savings from the new slack-time based algorithm is very closed to those from MILP. For c880, the energy saving is 22 % for subthreshold voltage operation and 50 % for nominal operation in PTM CMOS 90nm. For c2670 nominal voltage design, time of dual voltage optimization is reduced 44X compared to the MILP method. This new algorithm is beneficial for a large circuits with many large positive slack paths that would require enormous time for optimization by the MILP approach. I.

With transistor sizes being reduced to sub 45nm ranges, we have seen an improvement in speed, better performance, and deeper integration of digital circuits. However, there has been a corresponding increase in power consumption, along with greater energy dissipation. The reason is because of increased leakage current in the channel. A proposed solution is a shift towards high-k materials and metal gate from poly-silicon gate of yesteryear. Reduced feature sizes also suffer from greater parametric process variations during lithography and cause identical circuits to behave differently. With high-k technology overshadowing bulk technology ever since transistor sizes hit 45nm, a greater understanding of how the properties of high-k technology will affect digital devices especially their speed, power consumption, and energy dissipated upon voltage scaling is needed. Also, a better estimation of effects of parametric variations on circuits designed in high-k technology can provide valuable information which can be used to improve current designs.

Energy consumption of digital circuits has become a primary constraint in electronic design. The increasing popularity of the portable devices like smart phone, ipad, tablet and notebook has created an overwhelming demand for extended battery life of these devices. Numerous methods for energy reduction in CMOS circuits have been proposed in the literature. Power reduction techniques at various levels of abstraction are used in modern digital designs. Most popular techniques used include power gating, clock gating, multiple-supply voltages, multiple threshold devices. In this work we propose a technique to use dual supply voltages in digital designs in order to get a reduction in energy consumption. Three new algorithms are proposed for finding and assigning low voltage in dual voltage designs. Given a circuit and a supply voltage, the first algorithm finds a suitable value for a lower supply voltage and the other two algorithms assign that lower voltage to individual gates. A linear time algorithm described in the literature is used for computing slacks for all gates in a circuit for a given supply voltage. The slack of a gate is the difference between the critical path delay and the delay