Many code-generator generators use tree pattern matching and dynamic programming. This paper describes a simple program that generates matchers that are fast, compact, and easy to understand. It is simpler than common alternatives: 200–700 lines of Icon or 950 lines of C versus 3000 lines of C for Twig and 5000 for burg. Its matchers run up to 25 times faster than Twig’s, They are necessarily slower than burg’s BURS (bottom-up rewrite system) matchers, but they are more flexible and still practical. Categories and Subject Descriptors: D.3.4 [Programming Languages]: Processors—code gener-ation; compilers; translator writing systems and compiler generators

This document describes only that fraction of the BURS model that is required to use Burg. Readers interested in more detail might start with Reference [BDB90]. Other relevant documents include References [Kro75, HO82, HC86, Cha87, PLG88, PL87, BMW87, Hen89, FH91, Pro91]

Besides high code quality, a primary issue in embedded code generation is retargetability of code generators. This paper presents techniques for automatic generation of code selectors from externally specified processor models. In contrast to previous work, our retargetable compiler Record does not require tool-specific modelling formalisms, but starts from general HDL processor models. From an HDL model, all processor aspects needed for code generation are automatically derived. As demonstrated by experimental results, short turnaround times for retargeting are achieved, which permits to study the HW/SW trade-off between processor architectures and program execution speed.

ing with credit is permitted. To copy otherwise, to republish, to post on servers, or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from Publications Dept, ACM Inc., fax +1 (212) 869-0481, or permissions@acm.org. Optimal Code Selection in DAGs M. Anton Ertl Institut fur Computersprachen Technische Universitat Wien Argentinierstrae 8, 1040 Wien, Austria anton@mips.complang.tuwien.ac.at http://www.complang.tuwien.ac.at/anton/ Tel.: (+43-1) 58801 18515 Fax.: (+43-1) 58801 18598 Abstract We extend the tree parsing approach to code selection to DAGs. In general, our extension does not produce the optimal code selection for all DAGs (this problem would be NPcomplete) , but for certain code selection grammars, it does. We present a method for checking whether a code selection grammar belongs to this set of DAG-optimal grammars, and use this method to check code selection grammars adapted from lcc: the grammars for the MIPS and SPARC ...

. Many software compilers for embedded processors produce machine code of insufficient quality. Since for most applications software must meet tight code speed and size constraints, embedded software is still largely developed in assembly language. In order to eliminate this bottleneck and to enable the use of high-level language compilers also for embedded software, new code generation and optimization techniques are required. This paper describes a novel code generation technique for embedded processors with irregular data path architectures, such as typically found in fixed-point DSPs.The proposed code generation technique maps data flow graph representation of a program into highly efficient machine code for a target processor modeled by instruction set behavior. High code quality is ensured by tight coupling of different code generation phases. In contrast to earlier works, mainly based on heuristics, our approach is constraint-based. An initial set of constraints on code generati...

Abstract not found

Optimal instruction scheduling and register allocation are NP-complete problems that require heuristic solutions. By restricting the problem of register allocation and instruction scheduling for delayed-load architectures to expression trees we are able to find optimal schedules quickly. This thesis presents a fast, optimal code scheduling algorithm for processors with a delayed load of 1 instruction cycle. The algorithm minimizes both execution time and register use and runs in time proportional to the size of the expression tree. In addition, the algorithm is simple

Embedded systems have an extremely short time to market and therefore require easily retargetable compilers. Architecture description languages (ADLs) provide a single concise architecture specification for the generation of hardware, instruction set simulators and compilers. In this article, we present an ADL for compiler generation. From a specification, we can derive an optimized tree pattern matching instruction selector, a register allocator and an instruction scheduler. Compared to a hand-crafted back end, the generated compiler produces smaller and faster code. The ADL is rich enough that other tools, such as assemblers, linkers, simulators and documentation, can all be obtained from a single specification.

Code generation influences the efficiency of not only the compiled program but also the compilation process. The appearence of the many new processors has created the need of automating the code generation phase. The instruction selection is a important component to be poduced automatically in the code generation phase. The tools for automating the instruction selection usually use the tree-structure to represent the intermediate representation. The algorithms to manipulate the tree structure are simple. And the powerful tree rewriting tools can be automatically generated for transforming trees to target machine code. Among many technologies for the aumatic generation, BURS technology produces the fastest code generators. But, BURS technology often require long time and much space to process a complex machine description. Much efforts has gone to make BURS technology more attractive: efficient in points of time and space. In this proposal, we closely inspect BURS technology and propose...

: Many modern code generation methods use tree pattern matching with dynamic programming. However, especially in the case of an irregular special-purpose processor architecture their lack of transparency and stability may be problematic: it is difficult to predict the exact code generation result in advance, and the effects of a modification in the code generation rules may be surprisingly wide. In contrast, macro expansion techniques are intuitively transparent. When global variables are disallowed, macro expansion typically has the Church-Rosser property: the final expansion result is independent of the expansion order of the individual intermediate macro calls. Besides enabling parallel implementation, order-independence means stability: the effects of modifying a macro definition are guaranteed to remain local. The locality is actually the problem with macro expansion; code optimization is improved when an assembly language macro is sensitive to its context. For instance, it should...