Abstract. This paper presents our work towards a wearable autonomous microsystem for context recognition. The design process needs to take into account the properties ofa wearable environment in terms ofsensor placement for data extraction, energy harvesting, comfort and easy integration into clothes and accessories. We suggest to encapsulate the system in an embroidery or a button. The study ofa microsystem consisting ofa light sensor, a microphone, an accelerometer, a microprocessor and a RF transceiver shows that it is feasible to integrate such a system in a button-like form of 12 mm diameter and 4 mm thickness. We discuss packaging and assembly aspects ofsuch a system. Additionally, we argue that a solar cell on top ofthe button – together with a lithium polymer battery as energy storage – is capable to power the system even for a user who works predominantly indoors. 1

To explore integrated solar energy harvesting as a power source for low power systems such as wireless sensor nodes, an array of energy scavenging photodiodes based on a passive-pixel architecture for imagers and have been fabricated together with storage capacitors implemented using on-chip interconnect in a 0.35 μm CMOS logic process. Integrated vertical plate capacitors enable dense energy storage without limiting optical efficiency. Measurements show 225 μW/mm 2 output power generated by a light intensity of 20k LUX.

The continued drive toward technology scaling in VLSI design has provided greater integration levels in silicon chips. Thanks to the reduction in minimum feature size and the corresponding decrease in power supply voltage, digital circuits have bene-fited from savings in area and power consumption. This approach presents a number of challenges in Complementary Metal-Oxide Semiconductor (CMOS) analog circuit design. As the gate oxide of transistors becomes thinner and power consumption increases, a lower supply voltage must be used, even though it results in performance degradation of analog circuits. This must be done in order to avoid silicon punch-through. In applications requiring low power consumption and moderate conversion speed, one of the most frequently used analog-to-digital converter (ADC) architec-tures is the successive approximation. As data converters are mixed-signal circuits, containing both analog and digital circuits, they suffer from the same problems just described. This thesis presents the design of a low-voltage successive approximation ADC based on a Switched Opamp comparator. The proposed comparator archi-

Copyright c ○ 2005 by Phoebus Wei-Chih Chen

The rapid decreases in power consumption, size and cost along with dramatic increases in performance of communication, sensing and computation have led to the development of Smart Dust – millimeter-scale autonomous systems that form the basis of massive distributed wireless sensor networks [1]. Smart Dust motes contain digital control and processing, one or more sensors, sensor interface circuits including an ADC, wireless communication, and energy storage/power source (Fig. 17.4.1) – integrating a complete, complex system into a millimeter-scale volume. Sample applications include inventory control, smart office spaces, fingertip accelerometer virtual keyboards, defense networks that could be rapidly deployed by unmanned aerial vehicles (UAV), nodes that track the movements of birds, small animals, and even insects, and environmental networks that monitor conditions affecting crops and livestock.

Micro-sensor nodes are highly energy-constrained and have timevarying performance demands. Accordingly, in this work an ultralow-power energy-scalable ADC is presented. The SAR architecture is well suited to environment monitoring. Recent micropower implementations have been limited to low resolutions (8 bits) [1]. The circuit and architecture enhancements presented in this paper efficiently increase precision to 12 bits. The ADC has two resolution modes: 12b and 8b. In 12b mode, its sampling rate is scalable, at a constant FOM, from 0 to 100kS/s, and, in 8b mode, from 0 to 200kS/s. At the highest performance point (i.e., 12b, 100kS/s) the entire ADC (including all digital, analog, and reference circuitry) consumes 25µW from a 1V supply. Several techniques have enabled this low-voltage low-power performance. Analog offset calibration in the latch improves the comparator power-delay product; weak-inversion operation

A carbon nanotube is considered as a candidate for a next-generation chemical sensor. CNT sensors are attractive as they allow room-temperature sensing of chemicals. From the system perspective, this signifies that the sensor system does not require any micro hotplates, which are one of the major sources of power dissipation in other types of sensor systems. Nevertheless, a poor control of the CNT resistance poses a constraint on the attainable energy efficiency of the sensor platform. An investigation on the CNT sensors shows that the dynamic range of the interface should be 17 bits, while the resolution at each base resistance should be 7 bits. The proposed CMOS interface extends upon the previously published work to optimize the energy performance through both the architecture and circuit level innovations. The 17-bit dynamic range is attained by distributing the requirement into a 10-bit Analog-to-Digital Converter (ADC) and a 8-bit Digital-to-Analog Converter (DAC). An extra 1-bit leaves room for any unaccounted subblock performance error.

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