Abstract. Hard real-time systems must obey strict timing constraints. Therefore, one needs to derive guarantees on the worst-case execution times of a system’s tasks. In this context, predictable behavior of system components is crucial for the derivation of tight and thus useful bounds. This paper presents results about the predictability of common cache replacement policies. To this end, we introduce three metrics, evict, fill, and mls that capture aspects of cache-state predictability. A thorough analysis of the LRU, FIFO, MRU, and PLRU policies yields the respective values under these metrics. To the best of our knowledge, this work presents the first quantitative, analytical results for the predictability of replacement policies. Our results support empirical evidence in static cache analysis. 1

The use of cache memories challenges the design and verification of high-integrity systems by making WCET analysis and measurement, the central input to schedulability analysis, considerably more laborious and less robust. In this paper we identify the sources of instruction cacherelated variability and gage them with ad-hoc experiments. In that light, we perform a critical review of state-of-the-art approaches to coping with and reducing the unpredictability of cache behavior. Finally we single out practices and recommendations that we deem best fit to attack the sources of unpredictability and discuss their applicability to a real processor for use in European space industry. 1

Abstract: In this report, we propose to approach the problem of end-to-end performance achievement of real-time control loops in a global and system view. Conversely with the classical approach based on the separation of concerns between control and implementation, a coarser-grain view is investigated. The new approach is intended to be less architecture-dependent and able to provide the system with fault-tolerance abilities insuring robustness. Key-words: timing jitter. Aerospace computer control, real-time, robustness, performance evaluation, fault tolerance,

Caches are commonly employed to hide the latency gap between memory and the CPU by exploiting locality in memory accesses. On today’s architectures a cache miss may cost several hundred CPU cycles. In order to fulfill stringent performance requirements, caches are also used in hard real-time systems. In such systems, upper and lower bounds on the execution time of tasks have to be computed. Different methods have been proposed for timing analysis, including measurement and static analysis. The sensitivity of a cache replacement policy expresses to what extent the initial state of the cache may influence the number of cache hits and misses during program execution. We have developed a tool to precisely compute sensitivity properties for a large class of replacement policies including LRU, FIFO, PLRU, and MRU. Analysis results demonstrate that the initial state can have a strong impact on the cache performance if FIFO, PLRU, or MRU is used. A simple model of execution time is used to evaluate the impact of cache sensitivity on measured execution times. The model shows that underestimating the number of misses as strongly as is possible for FIFO, PLRU, and MRU may yield worstcase-execution-time estimates that are far wrong.