We present a high-speed range-imaging system based on a VLSI computational sensor developed in the CMU Computer Science Department. The VLSI range sensor is a custom chip consisting of an array of cells which combine photo-sensing and computation. Unlike conventional "step-and-repeat" lightstripe range finders, our sensor gathers range images in parallel as a scene is swept by a continuously moving plane of light. A prototype range-finding system has been built using a second-generation sensor and is capable of acquiring a 32 32 point frame of 3-D measurements in a millisecond --- two orders of magnitude faster than currently available range-finding systems. The accuracy and the repeatability of the acquired range data has been measured to be less than 0.2%. In this paper, we discuss the range-finding system and present experimental results that measure its performance. CMU Very Fast Range-Imaging System Shigeyuki Tada, Andrew Gruss and Takeo Kanade 10 October 1993 CMU-CS-93-179 T...

that of a biological vision. The two most critical features presently missing from the machine vision are lo}v latency processing and top-dow sen. sorv adaptation. This thesis proposes to overcome these two deficiencies by implementing global operations in computational sensors.

This report is a result of a workshop on Computational Sensors that was organized and held at The University of Pennsylvania on May 11-12, 1992. It presents a summary of the state of the art in computational sensors and recommendations for future research programs. Approximately 40 people were invited from academia, government, and industry. workshop hosted several key presentations and followed them with group discussion and summary sessions. Traditionally, sensory information processing proceeds in three steps: transducing (detection), read-out (and digitization), and processing (interpretation). Micro-electronics technologies have begun to spawn a new generation of sensors which combine transducing and processing on a single chip - a computational sensor. A computational sensor may attach analog or digital VLSI processing circuits to each use the physics of the underlying material for computation. Typically, a computational sensor implements a distributed computing model of the sensory data, including the where the data are sensed or preprocessed elsewhere. Combining computation and signal acquisition into a single chip results often in not only performance improvement but also totally new capabilities that were not previously possible. Finally, the workshop made several important recommendations.

A network of multi modal sensors with distributed and embedded computations is con-sidered for a video surveillance and monitoring application. Practical factors limiting the video surveillance of large areas are highlighted. A network of line-of-sight sensors and mobile-agents based computations are proposed to increase the e ectiveness. CMOS digi-tal cameras in which both sampling and quantization occur on the sensor focal plane are more suitable for this application. These cameras operate at very high video frame rates and are easily synchronized to acquire images synaptically across the entire network. Also, they feature highly localized short term memories and include some SIMD parallel computa-tions as an integral part of the image acquisition. This new framework enables distributed computation for piecewise stereovision across the camera network, enhanced spatio-temporal fusion, and super resolution imaging of steadily moving subjects. A top level description of the monitor, locate and track model of a surveillance and monitoring task is presented. A qualitative assessment of several key elements of the mobile agents based computation for tracking persistent tokens moving across the entire area is outlined. The idea is to have as

A prototype 32\Theta32 array processor fabricated in 2¯m CCD/CMOS technology implementing the multi-scale veto edge detection algorithm is presented. In this algorithm, differences between pixel values are computed in the original image, as well as after applying a series of smoothing filters of varying spatial scales. An edge exists between two pixels only if the magnitude of their difference is greater than a given threshold for all levels of smoothing tested. This algorithm maps particularly well to implementation as a focal plane processor as it requires only nearest neighbor communication. The CCD array performs the functions of image acquisition, charge loading and removal, and image smoothing. Analog circuits between each pair of pixels in the array compute the absolute value of difference between neighboring values and compare it to a global threshold. These circuits have been designed to allow reliable discrimination of differences from ¸ 3:1% to ¸ 10:1% of full scale range an...

This paper presents a systematic approach to design CMOS chips with concurrent picture acquisition and processing capabilities. These chips consist of regular arrangements of elementary units, called smart pixels. Light detection is made with vertical CMOS- BJTs connected in a Darlington structure. Pixel smartness is achieved by exploiting the Cellular Neural Network paradigm [1], [2], incorporating at each pixel location an analog computing cell which interacts with those of nearby pixels. We propose a current-mode implementation technique and give measurements from two 16 16 prototypes in a single-poly double-metal CMOS n-well 1.6m technology. In addition to the sensory and processing circuitry, both chips incorporate lightadaptation circuitry for automatic contrast adjustment. They obtain smart-pixel densities up to 89 units/mm 2 , with a power consumption down to 105W/unit and image processing times below 2s. Analog Current-Mode Design of Smart-Pixel Cellular Neural Network C...