We consider the problem of optimally allocating local feedback to the stages of a multistage amplifier. The local feedback gains affect many performance indexes for the overall amplifier, such as bandwidth, gain, rise time, delay, output signal swing, linearity, and noise performance, in a complicated and nonlinear fashion, making optimization of the feedback gains a challenging problem. In this paper, we show that this problem, though complicated and nonlinear, can be formulated as a special type of optimization problem called geometric programming. Geometric programs can be solved globally and efficiently using recently developed interior-point methods. Our method, therefore, gives a complete solution to the problem of optimally allocating local feedback gains, taking into account a wide variety of constraints. Index Terms---Amplifiers, analog circuits, circuit optimization, design automation, geometric programming, sensitivity. I.

T HE IMPORTANCE OF CMOS TECHNOLOGY is increasing in RF design applications owing to the promise of integrating electronic systems on a single silicon chip. While complete broad band characterization and accurate modeling of the MOSFET noise are critical requirements for circuit designs, the noise behavior and physics in short channel MOSFETs is not well understood. This dissertation explores the physical origin and contributing mechanisms of noise in MOSFETs, as well as a design methodology to minimize the impact of noise on fully integrated LNAs. Investigating the physical noise sources in the MOSFET imposes significant computational requirements, due to the multi-dimensional nature of the device. In addition, higher order transport models need to be considered due to aggressive channel-length scaling. This dissertation presents a quasi two-dimensional noise simulation technique which provides an accurate and fast solution for MOSFET noise analysis by combining a 1-D active transmission line model with rigorous 2-D device simulation. The physical origin of the excess noise in short channel MOSFETs has been identified. Source-side contributions dominate drain current noise; non-local transport behavior causes higher local ac resistance near the source junction and in turn generates extra noise contributions which are amplified by the channel transconductance. This phenomenon is directly reflected in excess values and a strong gate length dependence of # and # in scaled submicron MOSFETs. Higher order transport models are essential to capture this effect in v noise simulation. Contrary to the common assumption that drain current exhibits only 1/f and white channel thermal noise contributions, this study demonstrates that the substrate generates thermal fluctuations th...

Underlying physical mechanisms controlling the noise properties of oscillators are studied. This treatment shows the importance of inductance selection for oscillator noise optimization. A design strategy centered around an inductance selection scheme is executed using a practical graphical optimization method to optimize phase noise subject to design constraints such as power dissipation, tank amplitude, tuning range, startup condition, and diameters of spiral inductors. The optimization technique is demonstrated through a design example, leading to a 2.4-GHz fully integrated, LC voltage-controlled oscillator (VCO) implemented using 0.35- m MOS transistors. The measured phase-noise values are 121, 117, and 115 dBc/Hz at 600-kHz offset from 1.91, 2.03, and 2.60-GHz carriers, respectively. The VCO dissipates 4 mA from a 2.5-V supply voltage. The inversion mode MOSCAP tuning is used to achieve 26% of tuning range. Two figures of merit for performance comparison of various oscillators are introduced and used to compare this work to previously reported results.

Based on measured four-noise parameters and two-port noise theory, considerations for noise optimization of integrated low-noise amplifier (LNA) designs are presented. If arbitrary values of source impedance are allowed, optimal noise performance of the LNA is obtained by adjusting the source degeneration inductance. Even for a fixed source impedance, the integrated LNA can achieve near min by choosing an appropriate device geometry along with an optimal bias condition. An 800-MHz LNA has been implemented in a standard 0.24- m CMOS technology. The amplifier possesses a 0.9-dB noise figure with a 7.1-dBm third-order input intercept point, while drawing 7.5 mW from a 2.0-V power supply, demonstrating that the proposed methodology can accurately predict noise performance of integrated LNA designs.

Abstract—Long design cycles due to the inability to predict silicon realities are a well-known problem that plagues analog/RF integrated circuit product development. As this problem worsens for nanoscale IC technologies, the high cost of design and multiple manufacturing spins causes fewer products to have the volume required to support full-custom implementation. Design reuse and analog synthesis make analog/RF design more affordable; however, the increasing process variability and lack of modeling accuracy remain extremely challenging for nanoscale analog/RF design. We propose a regular analog/RF IC using metal-mask configurability design methodology Optimization with Recourse of Analog Circuits including Layout Extraction (ORACLE), which is a combination of reuse and shared-use by formulating the synthesis problem as an optimization with recourse problem. Using a two-stage geometric programming with recourse approach, ORACLE solves for both the globally optimal shared and application-specific variables. Furthermore, robust optimization is proposed to treat the design with variability problem, further enhancing the ORACLE methodology by providing yield bound for each configuration of regular designs. The statistical variations of the process parameters are captured by a confidence ellipsoid. We demonstrate ORACLE for regular Low Noise Amplifier designs using metal-mask configurability, where a range of applications share common underlying structure and application-specific customization is performed using the metal-mask layers. Two RF oscillator design examples are shown to achieve robust designs with guaranteed yield bound. Index Terms—Configurable design, optimization with recourse, robustness, statistical optimization. I.

Convex optimization has been used in signal processing for a long time to choose coefficients for use in fast (linear) algorithms, such as in filter or array design; more recently, it has been used to carry out (nonlinear) processing on the signal itself. Examples of the latter case include total variation denoising, compressed sensing, fault detection, and image classification. In both scenarios, the optimization is carried out on time scales of seconds or minutes and without strict time constraints. Convex optimization has traditionally been considered computationally expensive, so its use has been limited to applications where plenty of time is available. Such restrictions are no longer justified. The combination of dramatically increased computing power, modern algorithms, and new coding approaches has delivered an enormous speed increase, which makes it possible to solve modest-sized convex optimization problems on microsecond or millisecond time scales and with strict deadlines. This enables real-time convex optimization in signal processing.