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16
Optimal design of a CMOS opamp via geometric programming
 IEEE Transactions on ComputerAided Design
, 2001
"... We describe a new method for determining component values and transistor dimensions for CMOS operational ampli ers (opamps). We observe that a wide variety of design objectives and constraints have a special form, i.e., they are posynomial functions of the design variables. As a result the ampli er ..."
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Cited by 51 (10 self)
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We describe a new method for determining component values and transistor dimensions for CMOS operational ampli ers (opamps). We observe that a wide variety of design objectives and constraints have a special form, i.e., they are posynomial functions of the design variables. As a result the ampli er design problem can be expressed as a special form of optimization problem called geometric programming, for which very e cient global optimization methods have been developed. As a consequence we can e ciently determine globally optimal ampli er designs, or globally optimal tradeo s among competing performance measures such aspower, openloop gain, and bandwidth. Our method therefore yields completely automated synthesis of (globally) optimal CMOS ampli ers, directly from speci cations. In this paper we apply this method to a speci c, widely used operational ampli er architecture, showing in detail how to formulate the design problem as a geometric program. We compute globally optimal tradeo curves relating performance measures such as power dissipation, unitygain bandwidth, and openloop gain. We show how the method can be used to synthesize robust designs, i.e., designs guaranteed to meet the speci cations for a
Disciplined convex programming
 Global Optimization: From Theory to Implementation, Nonconvex Optimization and Its Application Series
, 2006
"... ..."
Robust analog/RF circuit design with projectionbased posynomial modeling
 IEEE/ACM ICCAD
, 2004
"... In this paper we propose a RObust Analog Design tool (ROAD) for posttuning analog/RF circuits. Starting from an initial design derived from hand analysis or analog circuit synthesis based on simplified models, ROAD extracts accurate posynomial performance models via transistorlevel simulation and ..."
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Cited by 19 (9 self)
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In this paper we propose a RObust Analog Design tool (ROAD) for posttuning analog/RF circuits. Starting from an initial design derived from hand analysis or analog circuit synthesis based on simplified models, ROAD extracts accurate posynomial performance models via transistorlevel simulation and optimizes the circuit by geometric programming. Importantly, ROAD sets up all design constraints to include largescale process variations to facilitate the tradeoff between yield and performance. A novel convex formulation of the robust design problem is utilized to improve the optimization efficiency and to produce a solution that is superior to other local tuning methods. In addition, a novel projectionbased approach for posynomial fitting is used to facilitate scaling to large problem sizes. A new implicit power iteration algorithm is proposed to find the optimal projection space and extract the posynomial coefficients with robust convergence. The efficacy of ROAD is demonstrated on several circuit examples. 1.
Bandwidth Extension in CMOS with Optimized OnChip Inductors
 IEEE Journal of SolidState Circuits
, 2000
"... We present a technique for enhancing the bandwidth of gigahertz broadband circuitry by using optimized onchip spiral inductors as shuntpeaking elements. The series resistance of the onchip inductor is incorporated as part of the load resistance to permit a large inductance to be realized with mi ..."
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Cited by 12 (3 self)
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We present a technique for enhancing the bandwidth of gigahertz broadband circuitry by using optimized onchip spiral inductors as shuntpeaking elements. The series resistance of the onchip inductor is incorporated as part of the load resistance to permit a large inductance to be realized with minimum area and capacitance. Simple, accurate inductance expressions are used in a lumped circuit inductor model to allow the passive and active components in the circuit to be simultaneously optimized. A quick and efficient global optimization method, based on geometric programming, is discussed. The bandwidth extension technique is applied in the implementation of a 2.125Gbaud preamplifier that employs a commongate input stage followed by a cascoded commonsource stage. Onchip shunt peaking is introduced at the dominant pole to improve the overall system performance, including a 40% increase in the transimpedance. This implementation achieves a 1.6k\Omega transimpedance and a 0.6 A i...
A CMOS frequency synthesizer with an injectionlocked frequency divider for a 5GHz wireless LAN receiver
 IEEE J. SolidState Circuits
, 2000
"... based frequency synthesizer is designed in a H PR m CMOS technology. The power consumption of the synthesizer is significantly reduced by using a tracking injectionlocked frequency divider (ILFD) as the first frequency divider in the PLL feedback loop. Onchip spiral inductors with patterned ground ..."
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Cited by 11 (1 self)
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based frequency synthesizer is designed in a H PR m CMOS technology. The power consumption of the synthesizer is significantly reduced by using a tracking injectionlocked frequency divider (ILFD) as the first frequency divider in the PLL feedback loop. Onchip spiral inductors with patterned ground shields are also optimized to reduce the VCO and ILFD power consumption and to maximize the locking range of the ILFD. The synthesizer consumes 25 mW of power of which only 3.8 mW is consumed by the VCO and the ILFD combined. The PLL has a bandwidth of 280 kHz and a phase noise of IHI dBc/Hz at 1 MHz offset frequency. The spurious sidebands at the center of adjacent channels are less than SR dBc. Index Terms—CMOS RF circuits, frequency synthesizers, injectionlocked frequency dividers, wireless LAN. I.
Optimal allocation of local feedback in multistage amplifiers via geometric programming
 IEEE Transactions on Circuits and Systems I
, 2001
"... We consider the problem of optimally allocating local feedback to the stages of a multistage amplifier. The local feedback gains affect many performance indices for the overall amplifier, such as bandwidth, gain, risetime, delay, output signal swing, linearity, and noise performance, in a complicat ..."
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Cited by 7 (4 self)
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We consider the problem of optimally allocating local feedback to the stages of a multistage amplifier. The local feedback gains affect many performance indices for the overall amplifier, such as bandwidth, gain, risetime, delay, output signal swing, linearity, and noise performance, in a complicated and nonlinear fashion, making optimization of the feedback gains a challenging problem. In this paper we show that this problem, though complicated and nonlinear, can be formulated as a special type of optimization problem called geometric programming. Geometric programs can be solved globally and efficiently using recently developed interiorpoint methods. Our method therefore gives a complete solution to the problem of optimally allocating local feedback gains, taking into account a wide variety of constraints. 1 1
Design and optimization of LC oscillators
, 1999
"... We present a method for optimizing and automating component and transistor sizing for CMOS LC oscillators. We observe that the performance measures can be formulated as posynomial functions of the design variables. As a result, the LC oscillator design problems can be posed as a geometric program, ..."
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Cited by 7 (2 self)
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We present a method for optimizing and automating component and transistor sizing for CMOS LC oscillators. We observe that the performance measures can be formulated as posynomial functions of the design variables. As a result, the LC oscillator design problems can be posed as a geometric program, a special type of optimization problem for which very efficient global optimization methods have recently been developed. The synthesis method is therefore fast, and determines the globally optimal design; in particular the final solution is completely independent of the starting point (which can even be infeasible), and infeasible specifications are unambiguously detected. We can rapidly compute globally optimal tradeoff curves between competing objectives such as phase noise and power.
ORACLE: Optimization with Recourse of Analog Circuits Including Layout Extraction
 In Proceedings of the 41th IEEE/ACM Design Automation Conference
, 2004
"... Long design cycles due to the inability to predict silicon realities is a wellknown problem that plagues analog/RF integrated circuit product development. As this problem worsens for technologies below 100nm, the high cost of design and multiple manufacturing spins causes fewer products to have the ..."
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Cited by 3 (3 self)
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Long design cycles due to the inability to predict silicon realities is a wellknown problem that plagues analog/RF integrated circuit product development. As this problem worsens for technologies below 100nm, the high cost of design and multiple manufacturing spins causes fewer products to have the volume required to support full custom implementation. Design reuse and analog synthesis make analog/RF design more a#ordable; however, the increasing process variability and lack of modeling accuracy remains extremely challenging for nanoscale analog/RF design. We propose an analog/RF circuit design methodology ORACLE, which is a combination of reuse and shareduse by formulating the synthesis problem as an optimization with recourse problem. Using a twostage geometric programming with recourse approach, ORACLE solves for both the globally optimal shared and applicationspecific variables. Concurrently, we demonstrate ORACLE for novel metalmask configurable designs, where a range of applications share common underlying structure and applicationspecific customization is performed using the metalmask layers. We also include the silicon validation of the metalmask configurable designs.
Design of posynomial models for mosfets: Symbolic regression using genetic algorithms
 Genetic Programming: Theory and Practice IV
, 2006
"... Summary. Starting from a broad description of analog circuit design in terms of topology design and sizing, we discuss the difficulties of sizing and describe approaches that are manual or automatic. These approaches make use of blackbox optimization techniques such as evolutionary algorithms or con ..."
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Cited by 1 (1 self)
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Summary. Starting from a broad description of analog circuit design in terms of topology design and sizing, we discuss the difficulties of sizing and describe approaches that are manual or automatic. These approaches make use of blackbox optimization techniques such as evolutionary algorithms or convex optimization techniques such as geometric programming. Geometric programming requires posynomial expressions for a circuit’s performance measurements. We show how a genetic algorithm can be exploited to evolve a posynomial expression (i.e. model) of transistor (i.e. mosfet) behavior more accurately than statistical techniques in the literature. 1
Regular Analog/RF Integrated Circuits Design Using Optimization With Recourse Including Ellipsoidal Uncertainty
, 2008
"... Abstract—Long design cycles due to the inability to predict silicon realities are a wellknown problem that plagues analog/RF integrated circuit product development. As this problem worsens for nanoscale IC technologies, the high cost of design and multiple manufacturing spins causes fewer products ..."
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Cited by 1 (0 self)
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Abstract—Long design cycles due to the inability to predict silicon realities are a wellknown problem that plagues analog/RF integrated circuit product development. As this problem worsens for nanoscale IC technologies, the high cost of design and multiple manufacturing spins causes fewer products to have the volume required to support fullcustom implementation. Design reuse and analog synthesis make analog/RF design more affordable; however, the increasing process variability and lack of modeling accuracy remain extremely challenging for nanoscale analog/RF design. We propose a regular analog/RF IC using metalmask configurability design methodology Optimization with Recourse of Analog Circuits including Layout Extraction (ORACLE), which is a combination of reuse and shareduse by formulating the synthesis problem as an optimization with recourse problem. Using a twostage geometric programming with recourse approach, ORACLE solves for both the globally optimal shared and applicationspecific variables. Furthermore, robust optimization is proposed to treat the design with variability problem, further enhancing the ORACLE methodology by providing yield bound for each configuration of regular designs. The statistical variations of the process parameters are captured by a confidence ellipsoid. We demonstrate ORACLE for regular Low Noise Amplifier designs using metalmask configurability, where a range of applications share common underlying structure and applicationspecific customization is performed using the metalmask layers. Two RF oscillator design examples are shown to achieve robust designs with guaranteed yield bound. Index Terms—Configurable design, optimization with recourse, robustness, statistical optimization. I.