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57
PowerAware CPU Utilization Control for Distributed RealTime Systems
, 2008
"... CPU utilization control has recently been demonstrated to be an effective way of meeting endtoend deadlines for distributed realtime systems running in unpredictable environments. However, current research on utilization control focuses exclusively on task rate adaptation, which cannot effectivel ..."
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CPU utilization control has recently been demonstrated to be an effective way of meeting endtoend deadlines for distributed realtime systems running in unpredictable environments. However, current research on utilization control focuses exclusively on task rate adaptation, which cannot effectively handle rate saturation and discrete task rates. Since the CPU utilization contributed by a realtime periodic task is determined by both its rate and execution time, CPU frequency scaling can be used to adapt task execution times for powerefficient utilization control. In this paper, we present a twolayer coordinated CPU utilization control architecture. The primary control loop uses frequency scaling to locally control the CPU utilization of each processor, while the secondary control loop adopts rate adaptation to control the utilizations of all the processors at the cluster level on a finer timescale. Both the two control loops are designed and coordinated based on wellestablished control theory for theoretically guaranteed control accuracy and system stability. Empirical results on a physical testbed demonstrate that our control solution outperforms a stateoftheart utilization control algorithm by having more accurate control and less power consumption.
EnergyEfficient Policies for Embedded Clusters
 In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES’05
, 2005
"... Abstract Power conservation has become a key design issue for many systems, including clusters deployed for embedded systems, where ..."
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Abstract Power conservation has become a key design issue for many systems, including clusters deployed for embedded systems, where
A unified approach to variable voltage scheduling for nonideal DVS processors
 IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems
, 2004
"... Abstract—Voltage scheduling is an essential technique used to exploit the benefit of dynamic voltagescaling processors.Though extensive research exists in this area, current processor limitations such as time and energy transition overhead and voltagelevel discretization are often dismissed as ins ..."
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Cited by 11 (1 self)
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Abstract—Voltage scheduling is an essential technique used to exploit the benefit of dynamic voltagescaling processors.Though extensive research exists in this area, current processor limitations such as time and energy transition overhead and voltagelevel discretization are often dismissed as insignificant.We show that for hard realtime applications, disregarding these details can lead to suboptimal or even invalid results.We propose two algorithms to account for these limitations.The first is a greedy approach, while the second is more complex, but can significantly reduce the system’s energy consumption.Through experimental results on both real and randomly generated systems, we show the effectiveness of both algorithms and explore what conditions make it beneficial to use the complex algorithm over the basic one. Index Terms—Embedded systems, lowpower design, power minimization, scheduling, simulation. I.
Monitoring of cache miss rates for accurate dynamic voltage and frequency scaling
 In Proceedings of the 12th Annual Multimedia Computing and Networking Conference
, 2005
"... Modern mobile processors offer dynamic voltage and frequency scaling, which can be used to reduce the energy requirements of embedded and realtime applications by exploiting idle CPU resources, while still maintaining all applications’ realtime characteristics. However, accurate predictions of tas ..."
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Cited by 10 (3 self)
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Modern mobile processors offer dynamic voltage and frequency scaling, which can be used to reduce the energy requirements of embedded and realtime applications by exploiting idle CPU resources, while still maintaining all applications’ realtime characteristics. However, accurate predictions of task runtimes are key to computing the frequencies and voltages that ensure that all tasks ’ realtime constraints are met. Past work has used feedbackbased approaches, where applications ’ past CPU utilizations are used to predict future CPU requirements. Inaccurate predictions in these approaches can lead to missed deadlines, less than expected energy savings, or large overheads due to frequent voltage and frequency changes. Previous solutions ignore other ‘indicators ’ of future CPU requirements, such as the frequency of I/O operations, memory accesses, or interrupts. This paper addresses this shortcoming for memoryintensive applications, where measured task runtimes and cache miss rates are used as feedback for accurate runtime predictions. Cache miss rates indicate the frequency of memory accesses and enable us to derive the latencies introduced by these operations. The results shown in this paper indicate improvements in the number of deadlines met and the amount of energy saved. 1
Minimizing CPU Energy in RealTime Systems with Discrete Speed Management
, 2008
"... This paper presents a general framework to analyze and design embedded systems minimizing the energy consumption without violating timing requirements. A set of realistic assumptions is considered in the model in order to apply the results in practical realtime applications. The processor is assume ..."
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Cited by 10 (1 self)
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This paper presents a general framework to analyze and design embedded systems minimizing the energy consumption without violating timing requirements. A set of realistic assumptions is considered in the model in order to apply the results in practical realtime applications. The processor is assumed to have as a set of discrete operating modes, each characterized by speed and power consumption. The energy overhead and the transition delay incurred during mode switches are considered. Task computation times are modeled with a part that scales with the speed and a part having a fixed duration, to take I/O operations into account. The proposed method allows to compute the optimal sequence of voltage/speed changes that approximates the minimum continuous speed which guarantees the feasibility of a given set of realtime tasks, without violating the deadline constraints. The analysis is performed both under fixed and dynamic priority assignments.
A Resource Reservation Algorithm for PowerAware Scheduling of Periodic and Aperiodic RealTime Tasks
 IEEE Trans. Computers
, 2006
"... Abstract—Power consumption is an important issue in the design of realtime embedded systems. As many embedded systems are powered by batteries, the goal is to extend the autonomy of the system as much as possible. To reduce power consumption, modern processors can change their voltage and frequency ..."
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Cited by 7 (0 self)
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Abstract—Power consumption is an important issue in the design of realtime embedded systems. As many embedded systems are powered by batteries, the goal is to extend the autonomy of the system as much as possible. To reduce power consumption, modern processors can change their voltage and frequency at runtime. A poweraware scheduling algorithm can exploit this capability to reduce power consumption while preserving the timing constraints of realtime tasks. In this paper, we present GRUBPA, a novel poweraware scheduling algorithm based on a resource reservation technique. In addition to providing temporal isolation and time guarantees and, unlike most of the poweraware algorithms proposed in the literature, GRUBPA can efficiently handle systems consisting of both hard and soft, aperiodic, sporadic, and periodic tasks. We compared our algorithm with existing poweraware scheduling algorithms on an extensive set of simulation experiments on synthetic task sets. The results show that the performance of our algorithm is in line with the stateoftheart poweraware algorithms. We also present the implementation of our algorithm in the Linux operating system and discuss practical implementation issues like switching overhead and power models. Finally, we show the results of experiments performed on a real testbed application. Index Terms—DVS, realtime, resourcereservation, scheduling, poweraware. Ç
A unified practical approach to stochastic dvs scheduling
 In EMSOFT ’07: Proceedings of the 7th ACM & IEEE international conference on Embedded software (New
"... This paper deals with energyaware realtime system scheduling using dynamic voltage scaling (DVS) for energyconstrained embedded systems that execute variable and unpredictable workloads. The goal is to design DVS schemes to minimize the expected energy consumption of the whole system while meetin ..."
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Cited by 7 (0 self)
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This paper deals with energyaware realtime system scheduling using dynamic voltage scaling (DVS) for energyconstrained embedded systems that execute variable and unpredictable workloads. The goal is to design DVS schemes to minimize the expected energy consumption of the whole system while meeting the deadlines of the tasks. Researchers have attempted to take advantage of stochastic information about workloads to achieve better energy savings, and accordingly, various stochastic DVS schemes have been proposed. However, the existing stochastic DVS schemes are based on much simplified power models that assume unrestricted continuous frequency, welldefined power/frequency relation, and no speed change overhead. When these schemes are used in practice, they need to be patched in order to comply with realistic power models. Experiments show that some of such DVS schemes perform even worse than certain nonstochastic DVS schemes. Furthermore, even for stochastic schemes that were shown experimentally to outperform nonstochastic schemes, it is not clear how well they perform compared to the optimal solution, which is yet to be found. In this work, we provide a unified practical approach for obtaining optimal (or provably close to optimal) stochastic intertask, intratask, and hybrid DVS schemes under realistic power models in which the processor only provides a set of discrete speeds, no assumption is made on power/frequency relation, and speed change overhead is considered. We also evaluate the existing DVS schemes by comparing them with our DVS schemes.
Contractbased Integration of Cyberphysical Analyses
 in Proceedings of the 14th International Conference on Embedded Software, ser. EMSOFT ’14
"... Developing cyberphysical systems involves multiple engineering domains, e.g., timing, logical correctness, thermal resilience, and mechanical stress. In today’s industrial practice, these domains rely on multiple analyses to obtain and verify critical system properties. Domain differences make th ..."
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Cited by 5 (4 self)
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Developing cyberphysical systems involves multiple engineering domains, e.g., timing, logical correctness, thermal resilience, and mechanical stress. In today’s industrial practice, these domains rely on multiple analyses to obtain and verify critical system properties. Domain differences make the analyses abstract away interactions among themselves, potentially invalidating the results. Specifically, one challenge is to ensure that an analysis is never applied to a model that violates the assumptions of the analysis. Since such violation can originate from the updating of the model by another analysis, analyses must be executed in the correct order. Another challenge is to apply diverse analyses soundly and scalably over models of realistic complexity. To address these challenges, we develop an analysis integration approach that uses contracts to specify dependencies between analyses, determine their correct orders of application, and specify and verify applicability conditions in multiple domains. We implement our approach and demonstrate its effectiveness, scalability, and extensibility through a verification case study for thread and battery cell scheduling.
Optimal Speed Assignment for Probabilistic Execution Times
 In 2 nd Workshop on PowerAware RealTime Computing (PARC’05), NJ
, 2005
"... The problem of reducing energy consumption is dominating the design and the implementation of embedded realtime systems. For this reason, a new generation of processors allow to vary the voltage and the operating frequency to balance computational speed versus energy consumption. The policies that c ..."
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Cited by 5 (3 self)
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The problem of reducing energy consumption is dominating the design and the implementation of embedded realtime systems. For this reason, a new generation of processors allow to vary the voltage and the operating frequency to balance computational speed versus energy consumption. The policies that can exploit this feature are called Dynamic Voltage Scheduling (DVS). In realtime systems, the DVS technique must also provide the worstcase computational requirement. However, it is well known that the probability of a task executing for the longest possible time is very low. Hence, DVS policies can exploit probabilistic information about the execution times of tasks to reduce the energy consumed by the processor. In this paper we provide the foundations to integrate probabilistic timing analysis with energy minimization techniques, starting from the simple case of one task. 1
ParaScale: Exploiting Parametric Timing Analysis for RealTime Schedulers and Dynamic Voltage Scaling
 Proceedings of the IEEE RealTime Systems Symposium
, 2005
"... Static timing analysis safely bounds worstcase execution times to determine if tasks can meet their deadlines in hard realtime systems. However, conventional timing analysis requires that the upper bound of loops be known statically, which limits its applicability. Parametric timing analysis metho ..."
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Cited by 4 (2 self)
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Static timing analysis safely bounds worstcase execution times to determine if tasks can meet their deadlines in hard realtime systems. However, conventional timing analysis requires that the upper bound of loops be known statically, which limits its applicability. Parametric timing analysis methods remove this constraint by providing the WCET as a formula parameterized on loop bounds. This paper contributes a novel technique to allow parametric timing analysis to interact with dynamic realtime schedulers. By dynamically detecting actual loop bounds, a lower WCET bound can be calculated, onthefly, for the remaining execution of a task. We analyze the benefits from parametric analysis in terms of dynamically discovered slack in a schedule. We then assess the potential for dynamic power conservation by exploiting parametric loop bounds for ParaScale, our intratask dynamic voltage scaling (DVS) approach. Our results demonstrate that the parametric approach to timing analysis provides 66%80% additional savings in power consumption. We further show that using this approach combined with online intratask DVS to exploit parametric execution times results in much lower power consumption. Hence, even in the absence of dynamic scheduling, significant savings in power can be obtained, e.g., in the case of cyclic executives. 1.