Silicon integrated circuit spiral inductors and transformers are analyzed using electromagnetic analysis. With appropriate approximations, the calculations are reduced to electrostatic and magnetostatic calculations. The important effects of substrate loss are included in the analysis. Classic circuit analysis and network analysis techniques are used to derive two-port parameters from the circuits. From two-port measurements, loworder, frequency-independent lumped circuits are used to model the physical behavior over a broad-frequency range. The analysis is applied to traditional square and polygon inductors and transformer structures as well as to multilayer metal structures and coupled inductors. A custom computer-aided-design tool called ASITIC is described, which is used for the analysis, design, and optimization of these structures. Measurements taken over a frequency range from 100 MHz to 5 GHz show good agreement with theory.

We present an efficient method for optimal design and synthesis of CMOS inductors for use in RF circuits. This method uses the the physical dimensions of the inductor as the design parameters and handles a variety of specifications including fixed value of inductance, minimum self-resonant frequency, minimum quality factor, etc. Geometric constraints that can be handled include maximum and minimum values for every design parameter and a limit on total area. Our method is based on formulating the design problem as a special type of optimization problem called geometric programming, for which powerful efficient interior-point methods have recently been developed. This allows us to solve the inductor synthesis problem globally and extremely efficiently. Also,we can rapidly compute globally optimal trade-off curves between competing objectives such as quality factor and total inductor area. We have fabricated a number of inductors designed by the method, and found good agreement between the experimental data and the specifications predicted by our method. 1

Injection-locked oscillators (ILO's) are investigated in a new theoretical approach. A first-order differential equation is derived for the noise dynamics of ILO's. A single-ended injection-locked frequency divider (SILFD) is designed in a 0.5-µm CMOS technology operating at 1.8 GHz with more than 190 MHz locking range while consuming 3 mW of power. A differential injection-locked frequency divider (DILFD) is designed in a 0.5-µm CMOS technology operating at 3 GHz and consuming 0.45 mW, with a 190 MHz locking range. A locking range of 370 MHz is achieved for the DILFD when the power consumption is increased to 1.2 mW.

With Q’s in the tens to hundreds of thousands, micromachined vibrating resonators are proposed as integratedcircuit-compatible tanks for use in the low phase-noise oscillators and highly selective filters of communications subsystems. To date, LF oscillators have been fully integrated using merged CMOS/microstructure technologies, and bandpass filters consisting of spring-coupled micromechanical resonators have been demonstrated in a frequency range from HF to VHF. In particular, two-resonator micromechanical bandpass filters have been demonstrated with frequencies up to 35 MHz, percent bandwidths on the order of 0.2%, and insertion losses less than 2 dB. Higher order three-resonator filters with frequencies near 455 kHz have also been achieved, with equally impressive insertion losses for 0.09 % bandwidths, and with more than 64 dB of passband rejection. Additionally, free-free-beam single-pole resonators have recently been realized with frequencies up to 92 MHz and ’s around 8000. Evidence suggests that the ultimate frequency range of this high- tank technology depends upon material limitations, as well as design constraints, in particular, to the degree of electromechanical coupling achievable in microscale resonators.

We present a technique for enhancing the bandwidth of gigahertz broad-band circuitry by using optimized on-chip spiral inductors as shunt-peaking elements. The series resistance of the on-chip inductor is incorporated as part of the load resistance to permit a large inductance to be realized with minimum area and capacitance. Simple, accurate inductance expressions are used in a lumped circuit inductor model to allow the passive and active components in the circuit to be simultaneously optimized. A quick and efficient global optimization method, based on geometric programming, is discussed. The bandwidth extension technique is applied in the implementation of a 2.125-Gbaud preamplifier that employs a common-gate input stage followed by a cascoded common-source stage. On-chip shunt peaking is introduced at the dominant pole to improve the overall system performance, including a 40% increase in the transimpedance. This implementation achieves a 1.6-k\Omega transimpedance and a 0.6- A i...

This paper presents a 12.4-mW front end for a 5-GHz wireless LAN receiver fabricated in a 0.24- m CMOS technology. It consists of a low-noise amplifier (LNA), mixers, and an automatically tuned third-order filter controlled by a low-power phaselocked loop. The filter attenuates the image signal by an additional 12 dB beyond what can be achieved by an image-reject architecture. The filter also reduces the noise contribution of the cascode devices in the LNA core. The LNA/filter combination has a noise figure of 4.8 dB, and the overall noise figure of the signal path is 5.2 dB. The overall IIP3 is 2 dBm. Index Terms---Automatic tuning, CMOS analog integrated circuits, high-frequency filters, HIPERLAN, image-reject circuits, low-noise amplifier (LNA), notch filter, receiver front end. I. INTRODUCTION T HE GROWING popularity of notebook computers demands high data-rate wireless LAN systems. Many existing wireless LAN systems operate in the 2.4-GHz ISM band. These products currently ach...

The drive toward the implementation and massive deployment of wireless sensor networks calls for ultra-low-cost and low-power nodes. While the digital subsystems of the nodes are still riding Moore's Law, there is no such trend regarding the performance of analog components. This work presents a fully integrated architecture of both digital and analog components (including local oscillator) that offers significant reduction in cost, size and power consumption of the overall node. While such a radical architecture cannot offer the reliable tuning of standard designs, it is shown that by using random network coding, a dense network of such nodes can achieve throughput linear in the number of channels available for communication. Moreover, the ratio of the achievable throughput of the untuned network to the throughput of a tuned network with perfect coordination is shown to be close to 1/ e. This work makes use of known results from network coding theory that show that throughput equal to the max-flow in a graph is achievable. However, the challenge here is finding the max-flow of the random graph corresponding to the network.

A fully integrated 5-GHz phase-locked loop (PLL) based frequency synthesizer is designed in a 0 24 m CMOS technology. The power consumption of the synthesizer is significantly reduced by using a tracking injection-locked frequency divider (ILFD) as the first frequency divider in the PLL feedback loop. On-chip spiral inductors with patterned ground shields are also optimized to reduce the VCO and ILFD power consumption and to maximize the locking range of the ILFD. The synthesizer consumes 25 mW of power of which only 3.8 mW is consumed by the VCO and the ILFD combined. The PLL has a bandwidth of 280 kHz and a phase noise of 101 dBc/Hz at 1 MHz offset frequency. The spurious sidebands at the center of adjacent channels are less than 54 dBc. Index Terms---CMOS RF circuits, frequency synthesizers, injection -locked frequency dividers, wireless LAN. I. INTRODUCTION T HE DEMAND for wireless local area network (WLAN) systems which can support data rates in excess of 20 Mb/s with ve...

Abstract—An overview on the use of microelectromechanical systems (MEMS) technologies for timing and frequency control is presented. In particular, micromechanical RF filters and reference oscillators based on recently demonstrated vibrating on-chip micromechanical resonators with Q’s>10,000 at 1.5 GHz, are described as an attractive solution to the increasing count of RF components (e.g., filters) expected to be needed by future multi-band wireless devices. With Q’s this high in onchip abundance, such devices might also enable a paradigmshift in the design of timing and frequency control functions, where the advantages of high-Q are emphasized, rather than suppressed (e.g., due to size and cost reasons), resulting in enhanced robustness and power savings. With even more aggressive three-dimensional MEMS technologies, even higher onchip Q’s have been achieved via chip-scale atomic physics packages, which so far have achieved Q’s>10 7 using atomic cells measuring only 10 mm 3 in volume, consuming just 5 mW of power, all while still allowing Allan deviations down to 10-11 at one hour. Keywords—MEMS, micromechanical, quality factor, resonator, oscillator, filter, wireless communications, mechanical circuit, chip-scale atomic clock, physics package. I.

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