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21
Statistical timing analysis for intradie process variations with spatial correlations
 International Conference on Computer Aided Design
, 2007
"... Process variations have become a critical issue in performance verification of highperformance designs. We present a new, statistical timing analysis method that accounts for inter and intradie process variations and their spatial correlations. Since statistical timing analysis has an exponential ..."
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Cited by 121 (6 self)
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Process variations have become a critical issue in performance verification of highperformance designs. We present a new, statistical timing analysis method that accounts for inter and intradie process variations and their spatial correlations. Since statistical timing analysis has an exponential run time complexity, we propose a method whereby a statistical bound on the probability distribution function of the exact circuit delay is computed with linear run time. First, we develop a model for representing inter and intradie variations and their spatial correlations. Using this model, we then show how gate delays and arrival times can be represented as a sum of components, such that the correlation information between arrival times and gate delays is preserved. We then show how arrival times are propagated and merged in the circuit to obtain an arrival time distribution that is an upper bound on the distribution of the exact circuit delay. We prove the correctness of the bound and also show how the bound can be improved by propagating multiple arrival times. The proposed algorithms were implemented and tested on a set of benchmark circuits under several process variation scenarios. The results were compared with Monte Carlo simulation and show an accuracy of 3.32 % on average over all test cases. 1
Gate Sizing Using Incremental Parameterized Statistical Timing Analysis
 In ICCAD
, 2005
"... Abstract — As technology scales into the sub90nm domain, manufacturing variations become an increasingly significant portion of circuit delay. As a result, delays must be modeled as statistical distributions during both analysis and optimization. This paper uses incremental, parametric statistical ..."
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Cited by 32 (2 self)
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Abstract — As technology scales into the sub90nm domain, manufacturing variations become an increasingly significant portion of circuit delay. As a result, delays must be modeled as statistical distributions during both analysis and optimization. This paper uses incremental, parametric statistical static timing analysis (SSTA) to perform gate sizing with a required yield target. Both correlated and uncorrelated process parameters are considered by using a firstorder linear delay model with fitted process sensitivities. The fitted sensitivities are verified to be accurate with circuit simulations. Statistical information in the form of criticality probabilities are used to actively guide the optimization process which reduces runtime and improves area and performance. The gate sizing results show a significant improvement in worst slack at 99.86 % yield over deterministic optimization. I.
Computation and refinement of statistical bounds on circuit delay
 Proc. 2003 Design Automation Conference
, 2003
"... The growing impact of withindie process variation has created the need for statistical timing analysis, where gate delays are modeled as random variables. Statistical timing analysis has traditionally suffered from exponential run time complexity with circuit size, due to arrival time dependencies ..."
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Cited by 30 (2 self)
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The growing impact of withindie process variation has created the need for statistical timing analysis, where gate delays are modeled as random variables. Statistical timing analysis has traditionally suffered from exponential run time complexity with circuit size, due to arrival time dependencies created by reconverging paths in the circuit. In this paper, we propose a new approach to statistical timing analysis that is based on statistical bounds of the circuit delay. Since these bounds have linear run time complexity with circuit size, they can be computed efficiently for large circuits. Since both a lower and upper bound on the true statistical delay is available, the quality of the bounds can be determined. If the computed bounds are not sufficiently close to each other, we propose a heuristic to iteratively improve the bounds using selective enumeration of the sample space with additional run time. We demonstrate that the proposed bounds have only a small error and that by carefully selecting an small set of nodes for enumeration, this error can be further improved.
Defining statistical sensitivity for timing optimization of logic circuits with largescale process and environmental variations,” Docket MC06172004P, Filed with the US Patent Office
, 2005
"... The largescale process and environmental variations for today’s nanoscale ICs are requiring statistical approaches for timing analysis and optimization. Significant research has been recently focused on developing new statistical timing analysis algorithms, but often without consideration for how o ..."
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Cited by 21 (3 self)
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The largescale process and environmental variations for today’s nanoscale ICs are requiring statistical approaches for timing analysis and optimization. Significant research has been recently focused on developing new statistical timing analysis algorithms, but often without consideration for how one should interpret the statistical timing results for optimization. In this paper [1] we demonstrate why the traditional concepts of slack and critical path become ineffective under largescale variations, and we propose a novel sensitivitybased metric to assess the “criticality ” of each path and/or arc in the statistical timing graph. We define the statistical sensitivities for both paths and arcs, and theoretically prove that our path sensitivity is equivalent to the probability that a path is critical, and our arc sensitivity is equivalent to the probability that an arc sits on the critical path. An efficient algorithm with incremental analysis capability is described for fast sensitivity computation that has a linear runtime complexity in circuit size. The efficacy of the proposed sensitivity analysis is demonstrated on both standard benchmark circuits and large industry examples. 1.
A heuristic for optimizing stochastic activity networks with applications to statistical digital circuit sizing
 IEEE Transactions on Circuits and SystemsI
, 2004
"... A deterministic activity network (DAN) is a collection of activities, each with some duration, along with a set of precedence constraints, which specify that activities begin only when certain others have finished. One critical performance measure for an activity network is its makespan, which is th ..."
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Cited by 12 (4 self)
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A deterministic activity network (DAN) is a collection of activities, each with some duration, along with a set of precedence constraints, which specify that activities begin only when certain others have finished. One critical performance measure for an activity network is its makespan, which is the minimum time required to complete all activities. In a stochastic activity network (SAN), the durations of the activities and the makespan are random variables. The analysis of SANs is quite involved, but can be carried out numerically by Monte Carlo analysis. This paper concerns the optimization of a SAN, i.e., the choice of some design variables that affect the probability distributions of the activity durations. We concentrate on the problem of minimizing a quantile (e.g., 95%) of the makespan, subject to constraints on the variables. This problem has many applications, ranging from project management to digital integrated circuit (IC) sizing (the latter being our motivation). While there are effective methods for optimizing DANs, the SAN optimization problem is much more difficult; the few existing methods cannot handle largescale problems.
CRISTA: A new paradigm for lowpower, variationtolerant, and adaptive circuit synthesis using critical path isolation
 IEEE Transactions on CAD of IC & S
, 2007
"... Design considerations for robustness with respect to variations and low power operations typically impose contradictory design requirements. Low power design techniques such as voltage scaling, dualV th etc. can have a large negative impact on parametric yield. In this paper, we propose a novel par ..."
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Cited by 11 (0 self)
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Design considerations for robustness with respect to variations and low power operations typically impose contradictory design requirements. Low power design techniques such as voltage scaling, dualV th etc. can have a large negative impact on parametric yield. In this paper, we propose a novel paradigm for lowpower variationtolerant circuit design, which allows aggressive voltage scaling. The principal idea is to (a) isolate and predict the set of possible paths that may become critical under process variations, (b) ensure that they are activated rarely, and (c) avoid possible delay failures in the critical paths by dynamically switching to twocycle operation (assuming all standard operations are single cycle), when they are activated. This allows us to operate the circuit at reduced supply voltage while achieving the required yield. Simulation results on a set of benchmark circuits at 70nm process technology show average power reduction of 60 % with less than 10 % performance overhead and 18 % overhead in diearea compared to conventional synthesis. Application of the proposed methodology to pipelined design is also investigated. 1.
Abstract Optimal Bus Sizing in Migration of Processor Design
"... The effect of wire delay on circuit timing typically increases when an existing layout is migrated to a new generation of process technology, because wire resistance and cross capacitances do not scale well. Hence, careful sizing and spacing of wires is an important task in migration of a processor ..."
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Cited by 6 (4 self)
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The effect of wire delay on circuit timing typically increases when an existing layout is migrated to a new generation of process technology, because wire resistance and cross capacitances do not scale well. Hence, careful sizing and spacing of wires is an important task in migration of a processor to next generation technology. In this paper, timing optimization of signal buses is performed by resizing and spacing individual bus wires, while the area of the whole bus structure is regarded as a fixed constraint. Four different objective functions are defined and their usefulness is discussed in the context of the layout migration process. The paper presents solutions for the respective optimization problems and analyzes their properties. In an optimallytuned bus layout, after optimizing the most critical signal delay, all signal delays (or slacks) are equal. The optimal solution of the MinMax problem is always bounded by the solution of the corresponding sumofdelays problem. An iterative algorithm to find the optimallytuned bus layout is presented. Examples of solutions are shown, and design implications are derived and discussed. 1
A yield model for integrated circuits and its application to statistical timing analysis
 IEEE Transactions on ComputerAided Design
"... Abstract—A model for processinduced parameter variations is proposed, combining dietodie, withindie systematic, and withindie random variations. This model is put to use toward finding suitable timing margins and device file settings, to verify whether a circuit meets a desired timing yield. Whi ..."
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Cited by 5 (1 self)
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Abstract—A model for processinduced parameter variations is proposed, combining dietodie, withindie systematic, and withindie random variations. This model is put to use toward finding suitable timing margins and device file settings, to verify whether a circuit meets a desired timing yield. While this parameter model is cognizant of withindie correlations, it does not require specific variation models, layout information, or prior knowledge of intrachip covariance trends. The approach works with a “generic ” critical path, leading to what is referred to as a “processspecific” statisticaltiminganalysis technique that depends only on the process technology, transistor parameters, and circuit style. A key feature is that the variation model can be easily built from process data. The derived results are “fullchip, ” applicable with ease to circuits with millions of components. As such, this provides a way to do a statistical timing analysis without the need for detailed statistical analysis of every path in the design. Index Terms—Correlations, dietodie variations, generic critical path, parametric yield, principal component analysis, statistical timing analysis, timing margin, virtual corner, withindie variations. I.
Fast Comparisons of Circuit Implementations
, 2005
"... Digital designs can be mapped to different implementations using diverse approaches, with varying cost criteria. Postprocessing transforms, such as transistor sizing, can significantly improve circuit performance by optimizing critical paths to meet timing specifications. However, most transistor ..."
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Cited by 5 (1 self)
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Digital designs can be mapped to different implementations using diverse approaches, with varying cost criteria. Postprocessing transforms, such as transistor sizing, can significantly improve circuit performance by optimizing critical paths to meet timing specifications. However, most transistor sizing tools have high execution times, and the possible delay gains due to sizing, and the associated costs are not known prior to sizing. In this paper, we present two metrics for comparing different implementations—the minimum achievable delay and the cost of achieving a target delay—and show how these can be estimated without running a sizing tool. Using these fast and accurate performance estimators, a designer can determine the tradeoffs between multiple functionally identical implementations, and size only the selected implementation.
Delay modeling and statistical design of pipelined circuit under process variation
 IEEE Trans. on ComputerAided Design of Integrated Circuits and Systems
, 2006
"... Abstract—Under interdie and intradie parameter variations, the delay of a pipelined circuit follows a statistical distribution. This paper presents analytical models to estimate yield for a pipelined design based on delay distributions of individual pipe stages. Using the proposed models, it is sh ..."
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Cited by 4 (0 self)
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Abstract—Under interdie and intradie parameter variations, the delay of a pipelined circuit follows a statistical distribution. This paper presents analytical models to estimate yield for a pipelined design based on delay distributions of individual pipe stages. Using the proposed models, it is shown that a change in logic depth and an imbalance between stage yields can improve the design yield and the area of a pipeline a circuit. A novel statistical methodology is developed to enhance yield of a pipelined circuit under an area constraint. Based on the concept of area borrowing, the results show that incorporating a proper imbalance among stage areas in a fourstage pipeline improves design yield up to 15.4 % for the same area (and reduces area up to 8.4 % under a yield constraint) compared with a balanced design. Index Terms—Gatelevel sizing, pipeline design, statistical delay variation, yield enhancement. I.