www.dcs.gla.ac.uk/∼jtod/ Hydra is a computer hardware description language that integrates several kinds of software tool (simulation, netlist generation and timing analysis) within a single circuit specification. The design language is inherently concurrent, and it offers black box abstraction and general design patterns that simplify the design of circuits with regular structure. Hydra specifications are concise, allowing the complete design of a computer system as a digital circuit within a few pages. This paper discusses the motivations behind Hydra, and illustrates the system with a significant portion of the design of a basic RISC processor.

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Certain programs making use of monads need to perform recursion over the values of monadic actions. Although the do-notation of Haskell provides a convenient framework for monadic programming, it lacks the generality to support such recursive bindings. In this paper, we describe an enhanced translation schema for the donotation and its integration into Haskell. The new translation allows variables to be bound recursively, provided the underlying monad comes equipped with an appropriate fixed-point operator.

In property-based formal verification, a natural question that often arises is 'Have we specified enough properties?' In this paper, we provide a way of approximating an answer to this question. We present a relatively cheap analysis that, given the interface of a design under verification, plus a formal safety property list, identifies cases where some outputs of the design are not constrained at all by the properties. For practical reasons, we also provide an easy way for the verification engineer to explicitly state that certain outputs are allowed to be underconstrained.

Abstract. For the memory intensive task of graph reduction, modern PCs are limited not by processor speed, but by the rate that data can travel between processor and memory. This limitation is known as the von Neumann bottleneck. We explore the effect of widening this bottleneck using a special-purpose graph reduction machine with wide, parallel memories. Our prototype machine – the Reduceron – is implemented using an FPGA, and is based on a simple template-instantiation evaluator. Running at only 91.5MHz on an FPGA, the Reduceron is faster than mature bytecode implementations of Haskell running on a 2.8GHz PC. 1

Abstract. We present a domain specific language, embedded in Haskell, for general purpose parallel programming on GPUs. Our intention is to explore the use of connection patterns in parallel programming. We briefly present our earlier work on hardware generation, and outline the current state of GPU architectures and programming models. Finally, we present the current status of the Obsidian project, which aims to make GPU programming easier, without relinquishing detailed control of GPU resources. Both a programming example and some details of the implementation are presented. This is a report on work in progress. 1

This thesis describes the implementation of Obsidian, an embedded language for data-parallel programming. The programming style used in Obsidian borrows many ideas from the hardware description language Lava. In lava combinators are are used to combine circuits into larger circuits. Obsidian uses the idea of combinators from Lava, but instead of circuits; data-parallel computations are described. From the high level descriptions of data-parallel computations expressed in Obsidian, C programs are generated for execution on an NVIDIA GPU (Graphics Processing Unit). Modern GPUs are becomming powerful parallel computers, this is giving rise to an entire field called the GPGPU (General-Purpose Computations on the GPU) field. This field driven by the desire to exploit the power of GPUs for general-purpose computations. Obsidian explores a high level programming style for expressing parallel computataions. The implementation of a number of sorting algorithms using Obsidian is also shown. This thesis touches on the areas of GPGPU, embedded languages and data-parallel programming.

1 Introduction In a LCF-like proof 2

When designing hardware systems, a variety of models and languages are available whose aim is to manage complexity by allowing specification of such systems at different abstraction levels. Languages such as Verilog and VHDL where designed with simulation in mind rather than synthesis and lack features such as parametrised complex circuit definitions, a must for the design of generic complex systems. A more modern approach is the use of functional languages for hardware description that take advantage of the inherent abstraction in this paradigm, resulting in a more concise and manageable description of the system. This paper gives an overview of different functional language implementations for hardware description, highlighting their historical significance in terms of their capabilities and design approach. We will compare and contrast different ways that certain features, such as circuit sharing, have been implemented in these.

Fourier transforms are critical in a variety of fields but in the past, they were rarely used in applications because of the big processing power required. However, the Cooley's and Tukey's development of the Fast Fourier Transform (FFT) vastly simplified this. A large number of FFT algorithms have been developed, amongst which are the radix-2 and the radix-2 . These are the ones that have been mostly used for practical applications due to their simple structure with constant butterfly geometry. Most of the research to date for the implementation and benchmarking of FFT algorithms have been performed using general purpose processors, Digital Signal Processors (DSPs) and dedicated FFT processor ICs but as FPGAs have developed they have become a viable solution for computing FFTs. In this paper, SharpHDL, an object oriented HDL, will be used to implement the two mentioned FFT algorithms and test their equivalence.