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A Survey of Power Estimation Techniques in VLSI Circuits
 IEEE Transactions on VLSI Systems
, 1994
"... With the advent of portable and highdensity microelectronic devices, the power dissipation of very large scale integrated (VLSI) circuits is becoming a critical concern. Accurate and efficient power estimation during the design phase is required in order to meet the power specifications without a c ..."
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Cited by 225 (16 self)
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With the advent of portable and highdensity microelectronic devices, the power dissipation of very large scale integrated (VLSI) circuits is becoming a critical concern. Accurate and efficient power estimation during the design phase is required in order to meet the power specifications without a costly redesign process. In this paper, we present a review/tutorial of the power estimation techniques that have recently been proposed. Invited, IEEE Trans. on VLSI, Dec. 1994. 1. Introduction The continuing decrease in feature size and the corresponding increase in chip density and operating frequency have made power consumption a major concern in VLSI design [1, 2]. Modern microprocessors are indeed hot: the PowerPC chip from Motorola consumes 8.5 Watts, the Pentium chip from Intel consumes 16 Watts, and DEC's alpha chip consumes 30 Watts. Excessive power dissipation in integrated circuits not only discourages their use in a portable environment, but also causes overheating, which degr...
minimization in IC Design: Principles and applications
 ACM Transactions on Design Automation of Electronic Systems
, 1996
"... Low power has emerged as a principal theme in today’s electronics industry. The need for low power has caused a major paradigm shift in which power dissipation is as important as performance and area. This article presents an indepth survey of CAD methodologies and techniques for designing low powe ..."
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Cited by 159 (29 self)
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Low power has emerged as a principal theme in today’s electronics industry. The need for low power has caused a major paradigm shift in which power dissipation is as important as performance and area. This article presents an indepth survey of CAD methodologies and techniques for designing low power digital CMOS circuits and systems and describes the many issues facing designers at architectural, logic and physical levels of design abstraction. It reviews some of the techniques and tools that have been proposed to overcome these difficulties and outlines the future challenges that must be met to design low power, high performance systems. 1.
A Monte Carlo Approach for Power Estimation
, 1993
"... Excessive power dissipation in integrated circuits causes overheating and can lead to soft errors and/or permanent damage. The severity of the problem increases in proportion to the level of integration, so that power estimation tools are badly needed for presentday technology. Traditional simulati ..."
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Cited by 101 (9 self)
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Excessive power dissipation in integrated circuits causes overheating and can lead to soft errors and/or permanent damage. The severity of the problem increases in proportion to the level of integration, so that power estimation tools are badly needed for presentday technology. Traditional simulationbased approaches simulate the circuit using test/functional input pattern sets. This is expensive and does not guarantee a meaningful power value. Other recent approaches have used probabilistic techniques in order to cover a large set of input patterns. However, they tradeoff accuracy for speed in ways that are not always acceptable. In this paper, we investigate an alternative technique that combines the accuracy of simulationbased techniques with the speed of the probabilistic techniques. The resulting method is statistical in nature; it consists of applying randomlygenerated input patterns to the circuit and monitoring, with a simulator, the resulting power value. This is continued...
SystemLevel Exploration for ParetoOptimal Configurations in Parameterized SystemsonaChip
, 2002
"... In this work, we provide a technique for efficiently exploring the power/performance design space of a parameterized systemonachip (SOC) architecture to find all Paretooptimal configurations. These Paretooptimal configurations will represent the range of power and performance tradeoffs that are ..."
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Cited by 40 (5 self)
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In this work, we provide a technique for efficiently exploring the power/performance design space of a parameterized systemonachip (SOC) architecture to find all Paretooptimal configurations. These Paretooptimal configurations will represent the range of power and performance tradeoffs that are obtainable by adjusting parameter values for a fixed application that is mapped on the SOC architecture. Our approach extensively prunes the potentially large configuration space by taking advantage of parameter dependencies. We have successfully applied our technique to explore Paretooptimal configurations of our SOC architecture for a number of applications.
Improving the accuracy of circuit activity measurement
 In Proceedings of DAC
, 1994
"... A novel measure of activity in digital circuits, called transition density, along with an e cient algorithm to compute the density at every circuit node, has been proposed in [1]. However, the e ciency of this algorithm is achieved at the cost of accuracy in the density values. This leaves much to b ..."
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Cited by 29 (0 self)
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A novel measure of activity in digital circuits, called transition density, along with an e cient algorithm to compute the density at every circuit node, has been proposed in [1]. However, the e ciency of this algorithm is achieved at the cost of accuracy in the density values. This leaves much to be desired for its use in applications which require more accurate activity measurements at each node in the circuit e.g., circuit optimization problems with a low power goal. The complexity of this problem lies in computing the Boolean di erence probabilities at each node of the circuit. In this paper, an e cient algorithm for computing these probabilities is described. This allows the activity measurements, within a circuit partition, to be carried out in a more e cient manner compared to the well known approach of computing these probabilities. Larger circuit partitions, where each node within a partition is solved accurately with respect to that partition, result in more accurate activity measurements. An e cient circuit partitioning algorithm, with the goal of maximizing the number of correlated nodes within each partition, has been developed. This allows more accurate measurements compared to a randomly selected set of partitions. These methods have been incorporated in an improved simulator for circuit activity measurement. Some results obtained on the ISCAS85 benchmark circuits are included. I.
Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program
 in Proc. of 16th International Conference on VLSI Design
, 2003
"... In the previous work, the problem of nding gate delays to eliminate glitches has been solved by linear programs (LP) requiring an exponentially large number of constraints. By introducing two additional variables per gate, namely, the fastest and the slowest arrival times, besides the gate delay,we ..."
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Cited by 18 (10 self)
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In the previous work, the problem of nding gate delays to eliminate glitches has been solved by linear programs (LP) requiring an exponentially large number of constraints. By introducing two additional variables per gate, namely, the fastest and the slowest arrival times, besides the gate delay,we reduce the number of the LP constraints to be linear in circuit size. For example, the 469gate c880 circuit requires 3,611 constraints as compared to the 6.95 million constraints needed with the previous method. The reduced constraints provably produce the same exact LP solution as obtained by the exponential set of constraints. For the rst time, we are able to optimize all ISCAS'85 benchmarks. For the c7552 circuit, when the input to output delay is constrained not to increase, a design with 366 delay bu ers consumes only 34 % peak and 38 % average power as compared to an unoptimized design. As shown in previous work, the use of delay bu ers is essential in this case. The practicality of the design is demonstrated by implementing an optimized 4bit ALU circuit for which the power consumption was obtained by a circuitlevel simulator. 1.
Power Estimation Techniques for Integrated Circuits
, 1995
"... With the advent of portable and highdensity microelectronic devices, the power dissipation of very large scale integrated (VLSI) circuits is becoming a critical concern. Accurate and eficient power estimation during the design phase is required in order to meet the power specifications without a co ..."
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Cited by 18 (0 self)
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With the advent of portable and highdensity microelectronic devices, the power dissipation of very large scale integrated (VLSI) circuits is becoming a critical concern. Accurate and eficient power estimation during the design phase is required in order to meet the power specifications without a costly redesign process. Recently, a variety of power estimation techniques have been proposed, most of which are based on: I the use of simplified delay models, and 2 modeling t 1 e longterm behavior of logic signals wit I! probabilities. The array of available techniques diger in subtle ways in the assumptions that they make, the accuracy that they provide, and the kinds of circuits that they apply to. In this tutorial, I will survey the many power estimation techniques that have been recently proposed and, in an attempt to make sense of all the variety, I will try to explain the diflerent assumptions on which these techniques are based, and the impact of these assumptions on their accuracy and speed.
Adaptive models for input data compaction for power simulators," To appear
 in Proceedings of the 2nd AsiaPaci c Design Automation Conference
, 1997
"... Abstract This paper presents an effective and robust technique for compacting a large sequence of input vectors into a much smaller input sequence so as to reduce the circuit/gate level simulation time by orders of magnitude and maintain the accuracy of the power estimates. In particular, this pape ..."
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Cited by 18 (11 self)
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Abstract This paper presents an effective and robust technique for compacting a large sequence of input vectors into a much smaller input sequence so as to reduce the circuit/gate level simulation time by orders of magnitude and maintain the accuracy of the power estimates. In particular, this paper introduces and characterizes a family of dynamic Markov trees that can model complex spatiotemporal correlations which occur during power estimation both in combinational and sequential circuits. As the results demonstrate, large compaction ratios of 12 orders of magnitude can be obtained without significant loss (less than 5% on average) in the accuracy of power estimates. I.
Low Power Architectural Design Methodologies
 PH.D THESIS, MEMORANDUM NO. UCB/ERL M94/62, 30TH
, 1994
"... In recent years, power consumption has become a critical design concern for many VLSI systems. Nowhere is this more true than for portable, batteryoperated applications, where power consumption has perhaps superceded speed and area as the overriding implementation constraint. This adds another de ..."
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Cited by 17 (0 self)
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In recent years, power consumption has become a critical design concern for many VLSI systems. Nowhere is this more true than for portable, batteryoperated applications, where power consumption has perhaps superceded speed and area as the overriding implementation constraint. This adds another degree of freedom  and complexity  to the design process and mandates the need for design techniques and CAD tools that address power, as well as area and speed. This thesis presents a methodology and a set of tools that support lowpower system design. Lowpower techniques at levels ranging from technology to architecture are presented and their relative merits are compared. Several case studies demonstrate that architecture and systemlevel optimizations offer the greatest opportunities for power reduction. A survey of existing power analysis tools, however, reveals a marked lack of powerconscious tools at these levels. Addressing this issue, a collection of techniques for modeling power at the registertransfer (RT) level of abstraction is described. These techniques model the impact of design complexity and signal activity on datapath, memory, control, and interconnect power consumption. Several VLSI design examples are used to verify the proposed tools, which exhibit near switchlevel accuracy at RTlevel speeds. Finally, an integrated design space exploration environment is described that spans several levels of abstraction and embodies many of the power optimization and analysis strategies presented in this thesis.
Dependency Preserving Probabilistic Modeling of Switching Activity using Bayesian Networks
, 2001
"... We propose a new switching probability model for combinational circuits using a LogicInducedDirectedAcyclicGraph(LIDAG) and prove that such a graph corresponds to a Bayesian Network guaranteed to map all the dependencies inherent in the circuit. This switching activity can be estimated by captur ..."
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Cited by 13 (5 self)
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We propose a new switching probability model for combinational circuits using a LogicInducedDirectedAcyclicGraph(LIDAG) and prove that such a graph corresponds to a Bayesian Network guaranteed to map all the dependencies inherent in the circuit. This switching activity can be estimated by capturing complex dependencies (spatiotemporal and conditional) among signals efficiently by local messagepassing based on the Bayesian networks. Switching activity estimation of ISCAS and MCNC circuits with random input streams yield high accuracy (average mean error=0.002) and low computational time (average time=3.93 seconds).