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31
Generalized constraint generation in the presence of nondeterministic parasitics
 In Proc. IEEE International Conference on Computer Aided Design
, 1996
"... In a constraintdriven layout synthesis environment, parasitic constraints are generated and implemented in each phase of the design process to meet a given set of performance specifications. The success of the synthesis phase depends in great part on the effectiveness and the generality of the cons ..."
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In a constraintdriven layout synthesis environment, parasitic constraints are generated and implemented in each phase of the design process to meet a given set of performance specifications. The success of the synthesis phase depends in great part on the effectiveness and the generality of the constraint generation process. None of the existing approaches to the constraint generation problem however are suitable for a number of parasitic effects in active and passive devices due to nondeterministic process variations. To address this problem a novel methodology is proposed based on the separation of all variables associated with nondeterministic parasitics, thus allowing the translation of the problem into an equivalent one in which conventional constrained optimization techniques can be used. The requirements of the method are a welldefined set of statistical properties for all parasitics and a reasonable degree of linearity of the performance measures relevant to design. 1
Laygen ii: automatic analog ics layout generator based on a template approach
 in Proceedings of the fourteenth international conference on Genetic and evolutionary computation conference, ser. GECCO ’12
"... This paper describes an innovative analog IC layout generation tool, LAYGEN II, based on evolutionary computation techniques. The designer provides the high level layout guidelines through an abstract layout template. The template contains placement and routing constrains independently from technolo ..."
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This paper describes an innovative analog IC layout generation tool, LAYGEN II, based on evolutionary computation techniques. The designer provides the high level layout guidelines through an abstract layout template. The template contains placement and routing constrains independently from technology, and can be used hierarchically in the definition of templates for complex circuits. LAYGEN II uses this expert knowledge to guide the evolutionary optimization kernels during the automatic layout generation in the target technology. The routing task of the proceeding can range from a templatebased approach to a full automatic generation, if only connectivity is provided. The LAYGEN II tool is demonstrated for the layout generation of two typical analog circuit structures and the results validated by Calibre ® design rule check tool.
General AC Constraint Transformation for Analog ICs
 PROC. OF THE 35TH DESIGN AUTOMATION CONFERENCE
, 1998
"... The problem of designing complex analog circuits is attacked using a hierarchical topdown, constraintdriven design methodology. In this methodology, constraints are propagated automatically from highlevel specifications to physical design through a sequence of gradual transformations. Constraint ..."
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The problem of designing complex analog circuits is attacked using a hierarchical topdown, constraintdriven design methodology. In this methodology, constraints are propagated automatically from highlevel specifications to physical design through a sequence of gradual transformations. Constraint transformation is a critical step in the methodology, since it determines in large part the degree to which specifications are met. In this paper we describe how constraint transformations can be efficiently carried out using hierarchical parameter modeling and constrained optimization techniques. The process supports complex highlevel specification handling and accounts for secondorder effects, such as interconnect parasitics and mismatches. The suitability of the approach is demonstrated through an 4th order active filter test case.
Simultaneous Handling of Symmetry, Common Centroid, and General Placement Constraints
"... Abstract—In today’s systemonchip designs, both digital and analog parts of a circuit will be implemented on the same chip. Parasitic mismatch induced by layout will affect circuit performance significantly for analog designs. Consideration of symmetry and common centroid constraints during placeme ..."
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Abstract—In today’s systemonchip designs, both digital and analog parts of a circuit will be implemented on the same chip. Parasitic mismatch induced by layout will affect circuit performance significantly for analog designs. Consideration of symmetry and common centroid constraints during placement can help to reduce these errors. Besides these two specific types of placement constraints, other constraints, such as alignment, abutment, preplace, and maximum separation, are also essential in circuit placement. In this paper, we will present a placement methodology that can handle all these constraints at the same time. To the best of our knowledge, this is the first piece of work that can handle symmetry constraint, common centroid constraint, and other general placement constraints, simultaneously. Experimental results do confirm the effectiveness and scalability of our approach in solving this mixed constraintdriven placement problem. Index Terms—Analog placement, common centroid constraints, constraint graph, corner block list, sequence pair (SP), symmetry constraints. I.
Analog Placement with Common Centroid and 1D Symmetry Constraints
, 2009
"... In this paper, we will present a placement method for analog circuits. We consider both common centroid and 1D symmetry constraints, which are the two most common types of placement requirements in analog designs. The approach is based on a symmetric feasible condition on the sequence pair repres ..."
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In this paper, we will present a placement method for analog circuits. We consider both common centroid and 1D symmetry constraints, which are the two most common types of placement requirements in analog designs. The approach is based on a symmetric feasible condition on the sequence pair representation that can cover completely the set of all placements satisfying the common centroid and 1D symmetry constraints. This condition is essential for a good searching process to solve the problem effectively. Symmetric placement is an important step to achieve matchings of other electrical properties like delay and temperature variation. We have compared our results with those presented in the most updated previous works. Significant improvements can be obtained by our approach in both common centroid and 1D symmetry placements, and we are the first who can handle both constraints simultaneously.
Analog Placement Based on SymmetryIsland Formulation
"... Abstract—To reduce the effect of parasitic mismatches and circuit sensitivity to thermal gradients or process variations for analog circuits, some pairs of modules need to be placed symmetrically with respect to a common axis, and the symmetric modules are preferred to be placed at closest proximity ..."
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Abstract—To reduce the effect of parasitic mismatches and circuit sensitivity to thermal gradients or process variations for analog circuits, some pairs of modules need to be placed symmetrically with respect to a common axis, and the symmetric modules are preferred to be placed at closest proximity for better electrical properties. Most previous works handle the problem with symmetry constraints by imposing symmetricfeasible conditions in floorplan representations and using cost functions to minimize the distance between symmetric modules. Such approaches are inefficient due to the large search space and cannot guarantee the closest proximity of symmetry modules. In this paper, we present the first lineartimepacking algorithm for the placement with symmetry constraints using the topological floorplan representations. We first introduce the concept of a symmetry island which is formed by modules of the same symmetry group in a single connected placement. Based on this concept and the B ∗tree representation, we propose automatically symmetricfeasible (ASF) B ∗trees to directly model the placement of a symmetry island. We then present hierarchical B ∗trees (HB ∗trees) which can simultaneously optimize the placement with both symmetry islands and nonsymmetric modules. Unlike the previous works, our approach can place the symmetry modules in a symmetry group in close proximity and significantly reduce the search space based on the symmetryisland formulation. In particular, the packing time for an ASFB ∗tree or an HB ∗tree is the same as that for a plain B ∗tree (only linear) and much faster than previous works. Experimental results show that our approach achieves the bestpublished quality and runtime efficiency for analog placement. Index Terms—Analog circuit, floorplanning, physical design, placement. I.
Symmetry Within the SequencePair Representation in the Context of Placement for Analog Design
, 2000
"... This paper addresses the problem of devicelevel placement for analog layout, focusing mainly on symmetryrelated aspects. Different from most of the existent analog placement approaches, employing basically simulated annealing optimization algorithms operating on flat (absolute) spatial representa ..."
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This paper addresses the problem of devicelevel placement for analog layout, focusing mainly on symmetryrelated aspects. Different from most of the existent analog placement approaches, employing basically simulated annealing optimization algorithms operating on flat (absolute) spatial representations [4], our model uses a more recent topological representation called sequencepair [14], which has the advantage of not being restricted to slicing floorplan topologies. In this paper, we are explaining how specific features essential to analog placement, as the ability to deal with complex symmetry constraints (for instance, an arbitrary number of symmetry groups of cells), can be easily handled by employing the sequencepair representation. Several analog examples substantiate the effectiveness of our placement tool, which is already in use in an industrial environment.
Compositional Design of Analog Systems Using Contracts
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AUTOMATED SYNTHESIS TOOLS FOR ANALOG & RF IC SOFTWARE DEFINABLE TRANSCEIVERS
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Cadence Design Systems
"... The problem of designing complex analog circuits is attacked using a hierarchical topdown, constraintdriven design methodology. In this methodology, constraints are propagated automatically from highlevel speci cations to physical design through a sequence of gradual transformations. Constraint tr ..."
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The problem of designing complex analog circuits is attacked using a hierarchical topdown, constraintdriven design methodology. In this methodology, constraints are propagated automatically from highlevel speci cations to physical design through a sequence of gradual transformations. Constraint transformation is a critical step in the methodology, since it determines in large part the degree to which speci cations are met. In this paper we describe how constraint transformations can be e ciently carried out using hierarchical parameter modeling and constrained optimization techniques. The process supports complex highlevel specication handling and accounts for secondorder e ects, such as interconnect parasitics and mismatches. The suitability of the approach is demonstrated through an 4 th order active lter test case. 1.