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25
Noise in deep submicron digital design
 in Proc. of the International Conference on ComputerAided Design (ICCAD
, 1996
"... As technology scales into the deep submicron regime, noise immunity is becoming a metric of comparable importance to area, timing, and power for the analysis and design of VLSI systems. This paper denes noise as it pertains to digital systems and addresses the technology trends which are bringing n ..."
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Cited by 62 (7 self)
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As technology scales into the deep submicron regime, noise immunity is becoming a metric of comparable importance to area, timing, and power for the analysis and design of VLSI systems. This paper denes noise as it pertains to digital systems and addresses the technology trends which are bringing noise issues to the forefront. The noise sources which are plaguing digital systems are explained. A metric referred to as noise stability is dened, and a static noise analysis methodology based on this metric is introduced to demonstrate how noise can be analyzed systematically. Analysis issues associated with onchip interconnect are also considered. This paper concludes with a discussion of the device, circuit, layout, and logic design issues associated with noise. 1
On the Exploration of the Solution Space in Analog Placement with Symmetry Constraints
 IEEE TRANSACTIONS ON COMPUTERAIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
, 2004
"... The traditional way of approaching placement problems in computeraided design (CAD) tools for analog layout is to explore an extremely large search space of feasible or unfeasible placement configurations, where the cells are moved in the chip plane (being even allowed to overlap in possibly illeg ..."
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Cited by 9 (2 self)
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The traditional way of approaching placement problems in computeraided design (CAD) tools for analog layout is to explore an extremely large search space of feasible or unfeasible placement configurations, where the cells are moved in the chip plane (being even allowed to overlap in possibly illegal ways) by a stochastic optimizer. This paper presents a novel exploration technique for analog placement operating on a subset of tree representations of the layout—called symmetricfeasible, where the typical presence of an arbitrary number of symmetry groups of devices is directly taken into account during the search of the solution space. The computation times exhibited by this novel approach are significantly better than those of the algorithms using the traditional exploration strategy. This superior efficiency is partly due to the use of segment trees, a data structure introduced by Bentley, mainly used in computational geometry.
Block Placement with Symmetry Constraints based on the Otree Nonslicing Representation
 Proceedings of the 37th ACM/IEEE Design Automation Conference
, 2000
"... The ordered tree (Otree) representation has recently gained much interest in layout design automation. Different from previous topological representations of nonslicing floorplans, the Otree representation is simpler, needs linear computation effort to generate a corresponding layout, and exhibit ..."
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Cited by 8 (2 self)
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The ordered tree (Otree) representation has recently gained much interest in layout design automation. Different from previous topological representations of nonslicing floorplans, the Otree representation is simpler, needs linear computation effort to generate a corresponding layout, and exhibits a smaller upperbound of possible configurations. This paper addresses the problem of handling symmetry constraints in the context of the Otree representation. This problem arises in analog placement, where symmetry is often used to match layoutinduced parasitics and to balance thermal couplings in differential circuits. The good performance of our placement tool dealing with several analog designs taken from industry proves the effectiveness of our technique. 1.
Synthesis tools for mixedsignal ICs: progress on frontend and backend strategies
 Proc. DAC
, 1996
"... Digital synthesis tools such as logic synthesis and semicustom layout have dramatically changed both the frontend (specification to netlist) and backend (netlist to mask) steps of the digital IC design process. In this tutorial, we look at the last decade’s worth of progress on analog circuit synth ..."
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Cited by 7 (4 self)
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Digital synthesis tools such as logic synthesis and semicustom layout have dramatically changed both the frontend (specification to netlist) and backend (netlist to mask) steps of the digital IC design process. In this tutorial, we look at the last decade’s worth of progress on analog circuit synthesis and layout tools. We focus on the frontend and backend of analog and mixedsignal IC design flows. The tutorial summarizes the problems for which viable solutions are emerging, and those which are still unsolved. 1
Generalized constraint generation in the presence of nondeterministic parasitics
 In Proc. IEEE International Conference on Computer Aided Design
, 1996
"... In a constraintdriven layout synthesis environment, parasitic constraints are generated and implemented in each phase of the design process to meet a given set of performance specifications. The success of the synthesis phase depends in great part on the effectiveness and the generality of the cons ..."
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Cited by 2 (2 self)
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In a constraintdriven layout synthesis environment, parasitic constraints are generated and implemented in each phase of the design process to meet a given set of performance specifications. The success of the synthesis phase depends in great part on the effectiveness and the generality of the constraint generation process. None of the existing approaches to the constraint generation problem however are suitable for a number of parasitic effects in active and passive devices due to nondeterministic process variations. To address this problem a novel methodology is proposed based on the separation of all variables associated with nondeterministic parasitics, thus allowing the translation of the problem into an equivalent one in which conventional constrained optimization techniques can be used. The requirements of the method are a welldefined set of statistical properties for all parasitics and a reasonable degree of linearity of the performance measures relevant to design. 1
Topological Placement with Multiple Symmetry Groups of Devices for Analog Layout Design
"... Abstract – This paper presents an improved topological algorithm for devicelevel analog placement with symmetry constraints. Based on the exploration of symmetricfeasible sequencepairs [1], the technique employs an efficient model of priority queue [3]. The use of this data structure entails a co ..."
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Cited by 2 (1 self)
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Abstract – This paper presents an improved topological algorithm for devicelevel analog placement with symmetry constraints. Based on the exploration of symmetricfeasible sequencepairs [1], the technique employs an efficient model of priority queue [3]. The use of this data structure entails a complexity of O(G·n log log n) for each code evaluation, where n and G are the numbers of devices and symmetry groups, which is better than the complexity of other existent topological placement algorithms supporting symmetry constraints. The computation times exhibited by this approach are significantly better than those of the algorithms using an exploration strategy based on the absolute representation, as well as those of other previous topological algorithms. 1.
Constraints Space Management for the Layout of Analog IC's
 In Proc. Design Automation & Test in Europe
, 1998
"... An automated technique to narrow down the number of constraints in analog layout is described. The set of most important layout constraints is determined, discarding unnecessary constraints. The method is based on principal component analysis of the sensitivity matrix. Experimental results suggest t ..."
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Cited by 2 (1 self)
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An automated technique to narrow down the number of constraints in analog layout is described. The set of most important layout constraints is determined, discarding unnecessary constraints. The method is based on principal component analysis of the sensitivity matrix. Experimental results suggest the effectiveness of the method with respect to parasitic estimation and to the error margin. The results are compared with human designers' art in handcrafted constraints confinement. 1. Introduction High performance analog IC layout is the more laborious part of an IC design task. The main problems in today's deepsubmicron layout design are stray parasitics, signal integrity and crosstalk, which forces the designers to adopt special strategies for stateoftheart analog design. Analog and mixed design are facing the problems of lowpower lowvoltage requirements, which further complicate analog layout. This generally results in costly iterations between behavioral and physical design, i...
Analog Layout Synthesis Recent Advances in Topological Approaches
"... Abstract—This paper gives an overview of some recent advances in topological approaches to analog layout synthesis and in layoutaware analog sizing. The core issue in these approaches is the modeling of layout constraints for an efficient exploration process. This includes fast checking of constrai ..."
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Cited by 1 (0 self)
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Abstract—This paper gives an overview of some recent advances in topological approaches to analog layout synthesis and in layoutaware analog sizing. The core issue in these approaches is the modeling of layout constraints for an efficient exploration process. This includes fast checking of constraint compliance, reducing the search space, and quickly relating topological encodings to placements. Sequencepairs, B*trees, circuit hierarchy and layout templates are described as advantageous means to tackle these tasks. I.
General AC Constraint Transformation for Analog ICs
 PROC. OF THE 35TH DESIGN AUTOMATION CONFERENCE
, 1998
"... The problem of designing complex analog circuits is attacked using a hierarchical topdown, constraintdriven design methodology. In this methodology, constraints are propagated automatically from highlevel specifications to physical design through a sequence of gradual transformations. Constraint ..."
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Cited by 1 (0 self)
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The problem of designing complex analog circuits is attacked using a hierarchical topdown, constraintdriven design methodology. In this methodology, constraints are propagated automatically from highlevel specifications to physical design through a sequence of gradual transformations. Constraint transformation is a critical step in the methodology, since it determines in large part the degree to which specifications are met. In this paper we describe how constraint transformations can be efficiently carried out using hierarchical parameter modeling and constrained optimization techniques. The process supports complex highlevel specification handling and accounts for secondorder effects, such as interconnect parasitics and mismatches. The suitability of the approach is demonstrated through an 4th order active filter test case.
Analog Placement with Common Centroid and 1D Symmetry Constraints
, 2009
"... In this paper, we will present a placement method for analog circuits. We consider both common centroid and 1D symmetry constraints, which are the two most common types of placement requirements in analog designs. The approach is based on a symmetric feasible condition on the sequence pair repres ..."
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Cited by 1 (1 self)
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In this paper, we will present a placement method for analog circuits. We consider both common centroid and 1D symmetry constraints, which are the two most common types of placement requirements in analog designs. The approach is based on a symmetric feasible condition on the sequence pair representation that can cover completely the set of all placements satisfying the common centroid and 1D symmetry constraints. This condition is essential for a good searching process to solve the problem effectively. Symmetric placement is an important step to achieve matchings of other electrical properties like delay and temperature variation. We have compared our results with those presented in the most updated previous works. Significant improvements can be obtained by our approach in both common centroid and 1D symmetry placements, and we are the first who can handle both constraints simultaneously.