This dissertation focuses on efficiently forming reduced-order models for large, linear dynamic systems. Projections onto unions of Krylov subspaces lead to a class of reducedorder models known as rational interpolants. The cornerstone of this dissertation is a collection of theory relating Krylov projection to rational interpolation. Based on this theoretical framework, three algorithms for model reduction are proposed. The first algorithm, dual rational Arnoldi, is a numerically reliable approach involving orthogonal projection matrices. The second, rational Lanczos, is an efficient generalization of existing Lanczos-based methods. The third, rational power Krylov, avoids orthogonalization and is suited for parallel or approximate computations. The performance of the three algorithms is compared via a combination of theory and examples. Independent of the precise algorithm, a host of supporting tools are also developed to form a complete model-reduction package. Techniques for choosing the matching frequencies, estimating the modeling error, insuring the model's stability, treating multiple-input multiple-output systems, implementing parallelism, and avoiding a need for exact factors of large matrix pencils are all examined to various degrees.

Interconnect has become the dominating factor in determining circuit performance and reliability in deep submicron designs. In this embedded tutorial, we first discuss the trends and challenges of interconnect design as the technology feature size rapidly decreases towards below 0.1 micron. Then, we present commonly used interconnect models and a set of interconnect design and optimization techniques for improving interconnect performance and reliability. Finally, we present comparisons of different optimization techniques in terms of their efficiency and optimization results, and show the impact of these optimization techniques on interconnect performance in each technology generation from the 0.35µm to 0.07µm projected in the National Technology Roadmap for Semiconductors.

In recent years, reduced-order modeling techniques based on Krylov-subspace iterations, especially the Lanczos algorithm and the Arnoldi process, have become popular tools to tackle the large-scale time-invariant linear dynamical systems that arise in the simulation of electronic circuits. This paper reviews the main ideas of reduced-order modeling techniques based on Krylov subspaces and describes the use of reduced-order modeling in circuit simulation. 1 Introduction Krylov-subspace methods, most notably the Lanczos algorithm [81, 82] and the Arnoldi process [5], have long been recognized as powerful tools for large-scale matrix computations. Matrices that occur in large-scale computations usually have some special structures that allow to compute matrix-vector products with such a matrix (or its transpose) much more efficiently than for a dense, unstructured matrix. The most common structure is sparsity, i.e., only few of the matrix entries are nonzero. Computing a matrix-vector pr...

In this paper we present a new algorithm for computing reduced-order models of interconnect which utilizes the dominant controllable subspace of the system. The dominant controllable modes are computed via a new iterative Lyapunov equation solver, Vector ADI. This new algorithm is as inexpensive as Krylov subspace-based moment matching methods, and often produces a better approximation over a wide frequency range. A spiral inductor and a transmission line example show this new method can be much more accurate than moment matching via Arnoldi.

Introduction modeling ofelectro-thWOzs processes becomes increasingly important during semiconductor device development. For example, with th decreasing size and growing complexity of micro-electronic and micro-electro-mech)D) (MEMS) systems,th power dissipation of integrated circuitshr become a critical concern. Due to th very hry clock frequencies,th power consumption of a modern microprocessor can exceed 50W.Th th)O5N influence uponth device caused byeach transistor'sself-h'SzxO and th th5NSz interactionwith tighac placedneigh)Dx(s devices cannot be neglected, because excessive temperatures may causeth malfunction of th device or even destroy it.ThzS5W)s' it is necessary to develop aelectro-thzsh model whel computes th dependence between power dissipation and temperature distribution over th device. Moreover,such hch transfer analysis needs to be done quickly in response to every design alteration.Th model must also provide good accuracy in order to return precise temperature value

In this paper, we describe the growing problems of noise in digital integrated circuits and the design tools and techniques used to ensure the noise immunity of digital designs. 1 Introduction Noise has become a metric in the design of digital integrated circuits of comparable importance to area, timing, and power for four principle reasons: increasing interconnect densities, faster clock rates, more aggressive use of highperformance circuit families, and scaling threshold voltages. Increasing interconnect densities imply a signi#cant increase in coupling capacitance as a fraction of self-capacitance. Faster clock rates imply faster on-chip slew times. These two e#ects combine to make capacitive coupling a growing source of noise on-chip. Many high-performance circuit styles try to speed up one transition #usually falling# at the expense of the other and assign logical evaluates to the faster edge. Any circuit that utilizes these techniques we refer to as a skewed-evaluate circuit #e....

This paper demonstrates that, in general, implementations of circuit reduction methods can produce unstable and non-passive models even when such outcomes are theoretically proven to be impossible. The reason for this apparent contradiction is the numeric roundoff inherent in any finite-precision computer implementation. This paper introduces a new variant of the symmetric, multiport, Pad'e via Lanczos algorithm (SyMPVL) that, even in practice, is guaranteed to produce stable and passive models for all the circuits characterized by pairs of symmetric, positive semidefinite matrices. The algorithm is based by a new band Lanczos process with coupled recurrences. A number of circuit examples are used to illustrate the results. Introduction In recent years, model reduction for extracted RC(L) circuits has become an important part of the VLSI design methodology. Parasitic extraction programs typically produce large lumped RC (or even RLC) circuits as models of the structures that link the ...

Symbolic analog-circuit analysis has many applications, and is especially useful for analog synthesis and testability analysis. Existing approaches rely on two forms of symbolic expression representation: expanded sum-of-product form or arbitrarily nested form. Expanded form suffers the problem that the number of product terms grows exponentially with the size of a circuit, and approximation has to be used. Nested form is not canonical, i.e., many representations exist for a symbolic expression, and manipulations with the nested form are often complicated. In this paper, we present a new approach to exact and canonical symbolic analysis by exploiting the sparsity and sharing of product terms. It consists of representing the symbolic determinant of a circuit matrix by a graph---called determinant decision diagram (DDD)---and performing symbolic analysis by graph manipulations. We showed that DDD construction, as well as many symbolic analysis algorithms, can be performed in time complex...

This paper studies a general projection technique based on block Krylov subspaces for the computation of reduced-order models of multi-port RLC circuits. We show that the resulting reduced-order models are always passive, yet they still match at least half as many moments as the corresponding reduced-order models based on matrixPad 'e approximation. Moreover, for the special cases of RC, RL, and LC circuits, the reduced-order models obtained by projection and by matrix-Pad'e approximation are identical. For general RLC circuits, we show how the projection technique can easily be incorporated into the SyMPVL algorithm to obtain passive reduced-order models, in addition to the high-accuracy matrix-Pad'e approximation that characterizes SyMPVL, at essentially no extra computational costs. Connections between SyMPVL and the recently proposed reduced-order modeling algorithm PRIMA are also discussed. Numerical results for interconnect simulation problems are reported. 1 Introduction Electr...

Krylov-subspace based methods for generating low-order models of complicated interconnect are extremely effective, but there is no optimality theory for the resulting models. Alternatively, methods based on truncating a balanced realization (TBR), in which the observability and controllability gramians have been diagonalized, do have an optimality property but are too computationally expensive to use on complicated problems. In this paper we present a method for computing reduced-order models of interconnect by projection via the orthogonalized union of the approximate dominant eigenspaces of the system's controllability and observability gramians. The approximate dominant eigenspaces are obtained efficiently using an iterative Lyapunov equation solver, Vector ADI, which requires only linear matrix-vector solves. A spiral inductor and a transmission line example are used to demonstrate that the new method accurately approximates the TBR results and gives much more accurate wideband models than Krylov subspace-based moment matching methods.