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Design of a Secure, Intelligent, and Reconfigurable Web Cam Using a C Based System Design Flow
- In Thirty-Fifth Asilomar Conference on Signals, Systems and Computers, IEEE, Piscataway, NJ, USA
, 2001
"... This paper describes the design of a reconfigurable Internet camera, Cam-E-leon, combining reconfigurable hardware and embedded software. The software is based on the Clinux operating system. The network appliance implements a secure VPN (Virtual Private Network) with 3DES encryption and Internet ca ..."
Abstract
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Cited by 4 (2 self)
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This paper describes the design of a reconfigurable Internet camera, Cam-E-leon, combining reconfigurable hardware and embedded software. The software is based on the Clinux operating system. The network appliance implements a secure VPN (Virtual Private Network) with 3DES encryption and Internet camera server (including JPEG compression). The appliance's hardware can be reconfigured at run-time by the client, thus allowing to switch between several available image manipulation functions. This paper focuses on the design process used to implement the appliance starting from a high-level executable specification. 1.
Design Technology for Networked Reconfigurable FPGA Platforms
, 2002
"... Future networked appliances should be able to download new services or upgrades from the network and execute them locally. This flexibility is typically achieved by processors that can download new software over the network, using JAVA technology. This paper demonstrates that FPGAs are a realistic i ..."
Abstract
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Cited by 3 (0 self)
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Future networked appliances should be able to download new services or upgrades from the network and execute them locally. This flexibility is typically achieved by processors that can download new software over the network, using JAVA technology. This paper demonstrates that FPGAs are a realistic implementation platform for thin server or client applications. FPGAs can offer the same end-user experience as software based systems, combined with more computational power and lower cost.
A Design Methodology for Construction of Asynchronous Pipelines with Handel-C
- IEEE Software
, 1988
"... CSP channels are proposed as a means of developing high-level, asynchronous pipeline architectures over and above existing synchronous logic. Channel-based design allows hardware systems to be designed and constructed using top-down software engineering methods, which have not previously been availa ..."
Abstract
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Cited by 1 (0 self)
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CSP channels are proposed as a means of developing high-level, asynchronous pipeline architectures over and above existing synchronous logic. Channel-based design allows hardware systems to be designed and constructed using top-down software engineering methods, which have not previously been available within hardware-software co-design. The intention is to enhance support for future large-scale co-designs. The design methodology and its performance implications are demonstrated through an exemplar, pipelined design of the Karhunen-Love Transform (KLT) algorithm, implemented using the Handel-C silicon compiler applied to dense FPGAs. 2 1
OCCN: a NoC modeling framework for design exploration
- Journal of Systems Architecture
, 2004
"... The On-Chip Communication Network (OCCN) project provides an efficient framework, developed within SourceForge, for the specification, modeling, simulation, and design exploration of network on-chip (NoC) based on an object-oriented C++ library built on top of SystemC. OCCN is shaped by our experien ..."
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Cited by 1 (0 self)
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The On-Chip Communication Network (OCCN) project provides an efficient framework, developed within SourceForge, for the specification, modeling, simulation, and design exploration of network on-chip (NoC) based on an object-oriented C++ library built on top of SystemC. OCCN is shaped by our experience in developing communication architectures for different System-on-Chip (SoC). OCCN increases the productivity of developing communication driver models through the definition of a universal Application Programming Interface (API). This API provides a new design pattern that enables creation and reuse of executable transaction level models (TLMs) across a variety of SystemC-based environments and simulation platforms. It also addresses model portability, simulation platform independence, interoperability, and high-level performance modeling issues. 1.
Object-Oriented High-Level Modeling of an InfiniBand to PCI-X Bridge
"... The rapid increase in the complexity of modern ASICs raises the need for an increase in the abstraction level used to design these chips. While there exist many offerings of tools and languages designed to raise the level of abstraction in ASIC design, their use in current design is very limited. ..."
Abstract
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The rapid increase in the complexity of modern ASICs raises the need for an increase in the abstraction level used to design these chips. While there exist many offerings of tools and languages designed to raise the level of abstraction in ASIC design, their use in current design is very limited.

