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A PseudoHierarchical Methodology for HighPerformance Microprocessor Design
 Proceedings of the International Symposium on Physical Design
, 1997
"... Abstract This paper reports on a highly effective methodology to construct complex high performance microprocessors. Critical aspects of the methodology include an integrated database for design control, algorithmic power grid generation, fully customized clock network insertion, timing driven plac ..."
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Abstract This paper reports on a highly effective methodology to construct complex high performance microprocessors. Critical aspects of the methodology include an integrated database for design control, algorithmic power grid generation, fully customized clock network insertion, timing driven placement and routing, an integrated timing closure strategy, and incremental checking that includes formal netlist verification, DRC and LVS. The methodology places particular emphasis on continuously improving the integration process and incrementally improving both the design and the interoperability of the tools. The final chip tapeout was 17 calendar days from the final netlist. I.
A fast delay analysis algorithm for the hybrid structured clock network
 in Proc. Int. Conf. Computer Design (ICCD
, 2004
"... This paper presents a novel approach to reducing the complexity of the transient linear circuit analysis for a hybrid structured clock network. Topology reduction is first used to reduce the complexity of the circuits and a preconditioned Krylovsubspace iterative method is then used to perform the ..."
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This paper presents a novel approach to reducing the complexity of the transient linear circuit analysis for a hybrid structured clock network. Topology reduction is first used to reduce the complexity of the circuits and a preconditioned Krylovsubspace iterative method is then used to perform the nodal analysis on the reduced circuits. By proper choice of the simulation time step based on Elmore delay model, the delay of the clock signal between the clock source and the sink node and the skews between the sink nodes can be obtained efficiently and accurately. Our experimental results show that the proposed algorithm is two orders of magnitude faster than HSPICE without loss of accuracy and stability and the maximum error is within 0.4 % of the exact delay time. 1.
3.1 Reducing Clock Skew Variability via Cross Links
"... Increasingly significant variational effects present a great challenge for delivering desired clock skew reliably. Nontree clock network has been recognized as a promising approach to overcome the variation problem. Existing nontree clock routing methods are restricted to a few simple or regular st ..."
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Increasingly significant variational effects present a great challenge for delivering desired clock skew reliably. Nontree clock network has been recognized as a promising approach to overcome the variation problem. Existing nontree clock routing methods are restricted to a few simple or regular structures, and often consume excessive amount of wirelength. In this paper, we suggest to construct a low cost nontree clock network by inserting cross links in a given clock tree. The effects of the link insertion on clock skew variability are analyzed. Based on the analysis, we propose two link insertion schemes that can quickly convert a clock tree to a nontree with significantly lower skew variability and very limited wirelength increase. In these schemes, the complicated nontree delay computation is circumvented. Further,
Table 1 Notations in this work
"... 2 1 1,2 logic ff hold where Dlogic is the delay of the combinational logic block; CP is the clock period time; Dff is the propagation delay through the flipflop; Dsetup and Dhold are time for data to remain stable before and after the clock triggers respectively. Definition 1. Reliable Buffered Clo ..."
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2 1 1,2 logic ff hold where Dlogic is the delay of the combinational logic block; CP is the clock period time; Dff is the propagation delay through the flipflop; Dsetup and Dhold are time for data to remain stable before and after the clock triggers respectively. Definition 1. Reliable Buffered Clock Routing Tree Problem: Given clock source s0, clock sink location S ��{s 1, s2, … , sn}, and a set of skew constraints C = {ti − tj ∈ [−NSBij, PSBij]}, build up a clock routing tree and find a set of feasible buffer locations such that the skew between any sink pairs should satisfy skew constraints C, while the influence due to wire width variations is minimized.
A MultiLevel Transmission Line Network Approach for MultiGiga Hertz Clock Distribution
"... AbstractIn high performance systems, process variations and fluctuations of operating environments have significant impact on the clock skew. Recently, hybrid structures of Htree and mesh [2,15,18,19] were proposed to distribute the clock signal with a balanced Htree and lock the skew using the s ..."
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AbstractIn high performance systems, process variations and fluctuations of operating environments have significant impact on the clock skew. Recently, hybrid structures of Htree and mesh [2,15,18,19] were proposed to distribute the clock signal with a balanced Htree and lock the skew using the shunt effect of the mesh. However, in multigiga hertz regime, the RC model [15] of the mesh is no longer valid. The inductance effect of the mesh can even make the skew worse. In this paper, we investigate the use of a novel architecture which incorporates multiple level transmission line shunts to distribute global clock signal. We derive the analytical expression of the skew reduction contributed by the shunt of a transmission line with the length of an integral multiple of clock wavelength. Based on the analytical skew expression, we adopt convex programming techniques to optimize the wire widths of the multilevel transmission line network. Simulation results show that the multilevel network achieves below 4ps skew for 10GHz clock. I.
Hybrid Structured Clock Network Construction
, 2001
"... This paper hierarchically constructs a hybrid mesh/tree clock network structure consisting of overlying zeroskew clock meshes, with underlying zeroskew clock trees originating from the mesh nodes. We propose a mesh construction procedure, which guarantees zero skew under the Elmore delay model, us ..."
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This paper hierarchically constructs a hybrid mesh/tree clock network structure consisting of overlying zeroskew clock meshes, with underlying zeroskew clock trees originating from the mesh nodes. We propose a mesh construction procedure, which guarantees zero skew under the Elmore delay model, using a simple and efficient linear programming formulation. Buffers are inserted to reduce the transition time (or rise time). As a postprocessing step, wire width optimization under an accurate higherorder delay metric is performed to further minimize the transition time and propagation delay/skew. Experimental results show that the hybrid mesh/tree construction scheme can provide smaller propagation delay and transition time than a comparable clock tree.
ANALYSIS AND OPTIMIZATION OF VLSI CLOCK DISTRIBUTION NETWORKS FOR SKEW VARIABILITY REDUCTION Approved as to style and content by:
, 2004
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Fig.2. Linear Model of L and C Components.
"... After replacing all the capacitances and inductances in the network with their linear comparison models, a pure resistor equivalent network is obtained. We can then use Nodal Analysis to formulate the resulting resistor network. Note that the transient conductance of L and C shown in equation (4) an ..."
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After replacing all the capacitances and inductances in the network with their linear comparison models, a pure resistor equivalent network is obtained. We can then use Nodal Analysis to formulate the resulting resistor network. Note that the transient conductance of L and C shown in equation (4) and (5) is stamped in Gnxn below and transient current of L and C is stamped in the righthand side (RHS) of the equations (6). n t t