Results 1  10
of
16
Optimal Wire and Transistor Sizing for Circuits with NonTree Topology
 in Proc. Int. Conf. on Computer Aided Design
, 1997
"... Conventional methods for optimal sizing of wires and transistors use linear RC circuit models and the Elmore delay as a measure of signal delay. If the RC circuit has a tree topology the sizing problem reduces to a convex optimization problem which can be solved using geometric programming. The tree ..."
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Cited by 28 (11 self)
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Conventional methods for optimal sizing of wires and transistors use linear RC circuit models and the Elmore delay as a measure of signal delay. If the RC circuit has a tree topology the sizing problem reduces to a convex optimization problem which can be solved using geometric programming. The tree topology restriction precludes the use of these methods in several sizing problems of significant importance to highperformance deep submicron design including, for example, circuits with loops of resistors, e.g., clock distribution meshes, and circuits with coupling capacitors, e.g., buses with crosstalk between the lines. The paper proposes a new optimization method which can be used to address these problems. The method uses the dominant time constant as a measure of signal propagation delay in an RC circuit, instead of Elmore delay. Using this measure, sizing of any RC circuit can be cast as a convex optimization problem which can be solved using the recently developed efficient interi...
Reducing Clock Skew Variability via Cross Links
 IN PROCEEDINGS OF THE 41ST ANNUAL CONFERENCE ON DESIGN AUTOMATION
, 2004
"... Increasingly significant variational e#ects present a great challenge for delivering desired clock skew reliably. Nontree clock network has been recognized as a promising approach to overcome the variation problem. Existing nontree clock routing methods are restricted to a few simple or regular ..."
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Cited by 27 (6 self)
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Increasingly significant variational e#ects present a great challenge for delivering desired clock skew reliably. Nontree clock network has been recognized as a promising approach to overcome the variation problem. Existing nontree clock routing methods are restricted to a few simple or regular structures, and often consume excessive amount of wires. In this paper, we suggest to construct a low cost nontree clock network by inserting cross links in a given clock tree. The e#ect of the link insertion on clock skew variability is analyzed. Based on the analysis, two link insertion schemes are proposed. These methods can quickly convert a clock tree to a nontree with significantly lower skew variability and very small amount of extra wires. Further, they can be applied to the recently popular nonzero skew routing easily. Experimental results on benchmark circuits show that this approach can achieve significant skew variability reduction with less than 2% increase of wirelength.
Hybrid structured clock network construction
 Proceedings of the 2001 IEEE/ACM international conference on Computeraided design
, 2001
"... This paper hierarchically constructs a hybrid mesh/tree clock network structure consisting of overlying zeroskew clock meshes, with underlying zeroskew clock trees originating from the mesh nodes. We propose a mesh construction procedure, which guarantees zero skew under the Elmore delay model, us ..."
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Cited by 17 (0 self)
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This paper hierarchically constructs a hybrid mesh/tree clock network structure consisting of overlying zeroskew clock meshes, with underlying zeroskew clock trees originating from the mesh nodes. We propose a mesh construction procedure, which guarantees zero skew under the Elmore delay model, using a simple and efficient linear programming formulation. Buffers are inserted to reduce the transition time (or rise time). As a postprocessing step, wire width optimization under an accurate higherorder delay metric is performed to further minimize the transition time and propagation delay/skew. Experimental results show that the hybrid mesh/tree construction scheme can provide smaller propagation delay and transition time than a comparable clock tree. 1.
A Multiple Level Network Approach for Clock Skew Minimization Under Process Variations
"... In this paper, we investigate the effect of multilevel networks on clock skew. We first define the simplified RC circuit model of a hybrid clock mesh/tree structure. The skew reduction effects of shunt segments contributed by the mesh is derived analytically from the simplified model. The result ind ..."
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Cited by 10 (0 self)
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In this paper, we investigate the effect of multilevel networks on clock skew. We first define the simplified RC circuit model of a hybrid clock mesh/tree structure. The skew reduction effects of shunt segments contributed by the mesh is derived analytically from the simplified model. The result indicates that the skew decreases proportionally to the exponential of −Rs/R, where Rs is the driving resistance of the clock buffer at a leaf node in the clock tree and R is the resistance of a mesh segment. Based on our analysis, we propose a hybrid multilevel mesh and tree structure for global clock distribution. A simple optimization scheme is adopted to optimize the routing resource distribution of the multilevel mesh. Experimental results show that by adding a mesh to the bottomlevel leaves of an Htree, the clock skew can be reduced from 29.2 ps to 8.7 ps, and the multilevel networks with same total routing area can further reduce the clock skew by another 30%. We also discuss the inductive effect of the mesh. When the clock frequency is less than 2 GHz, the RC model remains valid for clock meshes with grounded shielding or using differential signals.
Process Variation Aware Clock Tree Routing (Extended Abstract)
, 2003
"... Bing Lu Cadence Design Sys. Inc. ..."
3A5 MeshWorks: An Efficient Framework for Planning, Synthesis and Optimization of Clock Mesh Networks
"... Abstract — A leaflevel clock mesh is known to be very tolerant to variations [1]. However, its use is limited to a few highend designs because of the high power/resource requirements and lack of automatic mesh synthesis tools [2]. Most existing works on clock mesh [1], [3]–[7] either deal with sem ..."
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Cited by 4 (1 self)
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Abstract — A leaflevel clock mesh is known to be very tolerant to variations [1]. However, its use is limited to a few highend designs because of the high power/resource requirements and lack of automatic mesh synthesis tools [2]. Most existing works on clock mesh [1], [3]–[7] either deal with semicustom design or perform optimizations on a given clock mesh. However, the problem of obtaining a good initial clock mesh has not been addressed. Similarly, the problem of achieving a smooth tradeoff between skew and power/resources has not been addressed adequately. In this work, we present MeshWorks, the first comprehensive automated framework for planning, synthesis and optimization of clock mesh networks with the objective of addressing the above issues. Experimental results suggest that our algorithms can achieve an additional reduction of 26 % in buffer area, 19 % in wirelength and 18 % in power, compared to the recent work of [7] with similar worst case maximum frequency under variation. I.
Timing–Driven Variation–Aware Nonuniform Clock Mesh Synthesis
"... Clock skew variations adversely affect timing margins, limiting performance, reducing yield, and may also lead to functional faults. Nontree clock distribution networks, such as meshes and crosslinks, are employed to reduce skew and also to mitigate skew variations. However, these networks incur an ..."
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Cited by 2 (2 self)
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Clock skew variations adversely affect timing margins, limiting performance, reducing yield, and may also lead to functional faults. Nontree clock distribution networks, such as meshes and crosslinks, are employed to reduce skew and also to mitigate skew variations. However, these networks incur an increase in dissipated power while consuming significant metal resources. Several methods have been proposed to trade off power and wires to reduce skew. In this paper, an efficient algorithm is presented to reduce skew variations rather than skew, and prioritize the algorithm for critical timing paths, since these paths are more sensitive to skew variations. The algorithm has been implemented for a standard 65 nm cell library using standard EDA tools, and has been tested on several benchmark circuits. As compared to other methods, experimental results show a 37 % average reduction in metal consumption and 39 % average reduction in power dissipation, while insignificantly increasing the maximum skew.
A fast delay analysis algorithm for the hybrid structured clock network
 in Proc. Int. Conf. Computer Design (ICCD
, 2004
"... This paper presents a novel approach to reducing the complexity of the transient linear circuit analysis for a hybrid structured clock network. Topology reduction is first used to reduce the complexity of the circuits and a preconditioned Krylovsubspace iterative method is then used to perform the ..."
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Cited by 1 (0 self)
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This paper presents a novel approach to reducing the complexity of the transient linear circuit analysis for a hybrid structured clock network. Topology reduction is first used to reduce the complexity of the circuits and a preconditioned Krylovsubspace iterative method is then used to perform the nodal analysis on the reduced circuits. By proper choice of the simulation time step based on Elmore delay model, the delay of the clock signal between the clock source and the sink node and the skews between the sink nodes can be obtained efficiently and accurately. Our experimental results show that the proposed algorithm is two orders of magnitude faster than HSPICE without loss of accuracy and stability and the maximum error is within 0.4 % of the exact delay time. 1.
Won’t OnChip Clock Calibration Guarantee Performance Boost and Product Quality?
"... Abstract—In today’s high performance (multiGHz) microprocessors ’ design, onchip clock calibration features are needed to compensate for electrical parameter variations as a result of manufacturing process variations. The calibration features allow performance boost after manufacturing test and ma ..."
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Cited by 1 (1 self)
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Abstract—In today’s high performance (multiGHz) microprocessors ’ design, onchip clock calibration features are needed to compensate for electrical parameter variations as a result of manufacturing process variations. The calibration features allow performance boost after manufacturing test and maintain such performance levels during normal operation, thus preserving product quality. This strategy has been proven successful commercially. In this paper, we discuss the impact on performance and product quality of both permanent and transient faults possibly affecting these calibration circuits during manufacturing and normal operation, respectively. In particular, we consider the case of an onchip clock calibration feature of a commercial high performance microprocessor. We will show that some possible permanent faults may render the onchip clock calibration schemes useless (in process variations ’ compensation), while it is impossible for common manufacturing testing to detect this incorrect behavior. This means that a faulty operating microprocessor may pass the testing phase and be put onto the market, with a consequent impact on product quality and increase in Defect Level. Similarly, we will show that some possible transient faults occurring during the microprocessor infield operation could defeat the purpose of onchip clock calibration, again resulting in faulty operation of the microprocessor. This has long range implications to microprocessors ’ design as well, considering that process variations on die, as well as across the process, would worsen with continued scaling. Proper strategies to test these clock calibration features and to guarantee their correct operation in the field cannot be ignored. Possible design approaches to solve this problem will be discussed. Index Terms—Reliability, testing, fault tolerance, VLSI. 1
Table 1 Notations in this work
"... 2 1 1,2 logic ff hold where Dlogic is the delay of the combinational logic block; CP is the clock period time; Dff is the propagation delay through the flipflop; Dsetup and Dhold are time for data to remain stable before and after the clock triggers respectively. Definition 1. Reliable Buffered Clo ..."
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2 1 1,2 logic ff hold where Dlogic is the delay of the combinational logic block; CP is the clock period time; Dff is the propagation delay through the flipflop; Dsetup and Dhold are time for data to remain stable before and after the clock triggers respectively. Definition 1. Reliable Buffered Clock Routing Tree Problem: Given clock source s0, clock sink location S ��{s 1, s2, … , sn}, and a set of skew constraints C = {ti − tj ∈ [−NSBij, PSBij]}, build up a clock routing tree and find a set of feasible buffer locations such that the skew between any sink pairs should satisfy skew constraints C, while the influence due to wire width variations is minimized.