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29
Energy minimization using multiple supply voltages
 In International Symposium on Low Power Electronics and Design
, 1996
"... AbstractWe present a dynamic programming technique for solving the multiple supply voltage scheduling problem in both nonpipelined and functionally pipelined datapaths. The scheduling problem refers to the assignment of a supply voltage level (selected from a xed and known number of voltage level ..."
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Cited by 124 (5 self)
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AbstractWe present a dynamic programming technique for solving the multiple supply voltage scheduling problem in both nonpipelined and functionally pipelined datapaths. The scheduling problem refers to the assignment of a supply voltage level (selected from a xed and known number of voltage levels) to each operation in a data ow graph so as to minimize the average energy consumption for given computation time or throughput constraints or both. The energy model is accurate and accounts for the input pattern dependencies, reconvergent fanout induced dependencies, and the energy cost of level shifters. Experimental results show that using three supply voltage levels on a number of standard benchmarks, an average energy saving of 40.19% (with a computation time constraint of 1.5 times the critical path delay) can be obtained compared to using a single supply voltage level.
Multilevel logic synthesis
 Proc. IEEE
"... A survey of logic synthesis techniques for multilevel combinational logic is presented. The goal is to provide more indepth background and perspective for people interested in pursuing or assessing some of the topics in this emerging field. Introductions, capsule summaries, and, in some cases, deta ..."
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Cited by 120 (20 self)
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A survey of logic synthesis techniques for multilevel combinational logic is presented. The goal is to provide more indepth background and perspective for people interested in pursuing or assessing some of the topics in this emerging field. Introductions, capsule summaries, and, in some cases, detailed analysis, of the synthesis methods which have become established as practically significant are provided. Also included are some methods which
Combinational Logic Synthesis for LUT Based Field Programmable Gate Arrays
 ACM Transactions on Design Automation of Electronic Systems
, 1996
"... The increasing popularity of the field programmable gatearray (FPGA) technology has generated a great deal of interest in the algorithmic study and tool development for FPGAspecific design automation problems. The most widely used FPGAs are LUT based FPGAs, in which the basic logic element is a Ki ..."
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Cited by 31 (10 self)
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The increasing popularity of the field programmable gatearray (FPGA) technology has generated a great deal of interest in the algorithmic study and tool development for FPGAspecific design automation problems. The most widely used FPGAs are LUT based FPGAs, in which the basic logic element is a Kinput oneoutput lookuptable (LUT) that can implement any Boolean function of up to K variables. This unique feature of the LUT has brought new challenges to logic synthesis and optimization, resulting in many new techniques reported in recent years. This article summarizes the research results on combinational logic synthesis for LUT based FPGAs under a coherent framework. These results were dispersed in various conference proceedings and journals and under various formulations and terminologies. We first present general problem formulations, various optimization objectives and measurements, then focus on a set of commonly used basic concepts and techniques, and finally summarize existing synthesis algorithms and systems. We classify and summarize the basic techniques into two categories, namely, logic optimization and technology mapping, and describe the existing algorithms and systems in terms of how they use the classified basic
Power Efficient Technology Decomposition and Mapping under an Extended Power Consumption Model
, 1994
"... We propose a new power consumption model which accounts for the power consumption at the internal nodes of a cmos gate. Next, we address the problem of minimizing the average power consumption during the technology dependent phase of logic synthesis. Our approach consists of two steps. In the first ..."
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Cited by 23 (6 self)
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We propose a new power consumption model which accounts for the power consumption at the internal nodes of a cmos gate. Next, we address the problem of minimizing the average power consumption during the technology dependent phase of logic synthesis. Our approach consists of two steps. In the first step, we generate a nand decomposition of an optimized Boolean network such that the sum of average switching rates for all nodes in the network is minimum. In the second step, we perform a power efficient technology mapping that finds a minimal power mapping for given timing constraints (subject to the unknown load problem). 1 Introduction With recent advances in microelectronic technology, smaller devices are now possible allowing more functionality on an integrated circuit (ic). Portable applications have shifted from conventional low performance products such as wristwatches and calculators to high throughput and computationally intensive products such as notebook computers and cellul...
Synthesis of Circuits with LowCost Concurrent Error Detection Based on BoseLin Codes
"... This paper presents a procedure for synthesizing sequential machines with concurrent error detection based on BoseLin codes. BoseLin codes are an efficient solution for providing concurrent error detection as they are separable codes and have a fixed number of check bits, independent of the number ..."
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Cited by 21 (3 self)
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This paper presents a procedure for synthesizing sequential machines with concurrent error detection based on BoseLin codes. BoseLin codes are an efficient solution for providing concurrent error detection as they are separable codes and have a fixed number of check bits, independent of the number of information bits. Furthermore, BoseLin code checkers have a simple structure as they are based on modulo operations. Procedures are described for synthesizing circuits in a way that their structure ensures that all singlepoint faults can only cause errors that are detected by a BoseLin code. This paper presents an efficient scheme for concurrent error detection in sequential circuits with no constraint on the state encoding. Concurrent error detection for both the state bits and the output bits is based on a BoseLin code and their checking is combined such that one checker suffices. Results indicate low area overhead. The cost of concurrent error detection is reduced significantly co...
Computing the Area versus Delay Tradeoff Curves in Technology Mapping
, 1995
"... We examine the problem of mapping a Boolean network using gates from a finite size cell library. The objective is to minimize the total gate area subject to constraints on signal arrival time at the primary outputs. Our approach consists of two steps: In the first step, we compute delay functions (w ..."
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Cited by 18 (5 self)
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We examine the problem of mapping a Boolean network using gates from a finite size cell library. The objective is to minimize the total gate area subject to constraints on signal arrival time at the primary outputs. Our approach consists of two steps: In the first step, we compute delay functions (which capture gate area  arrival time tradeoffs) at all nodes in the network, and in the second step we generate the mapping solution based on the computed delay functions and the required times at the primary outputs. For a NANDdecomposed tree, subject to load calculation errors, this two step approach finds the minimum area mapping satisfying a delay constraint if such solution exists. The algorithm has polynomial run time on a nodebalanced tree and is easily extended to mapping a directed acyclic graph (DAG). We also show how to account for the wire delays during the delay function computation step. Our results compare favorably with those of MIS2.2 mapper.
Timing and Area Optimization for StandardCell VLSI Circuit Design
, 1995
"... A standard cell library typically contains several versions of any given gate type, each of which has a different gate size. We consider the problem of choosing optimal gate sizes from the library to minimize a cost function (such as total circuit area) while meeting the timing constraints imposed o ..."
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Cited by 16 (1 self)
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A standard cell library typically contains several versions of any given gate type, each of which has a different gate size. We consider the problem of choosing optimal gate sizes from the library to minimize a cost function (such as total circuit area) while meeting the timing constraints imposed on the circuit. After
Booledozer: Logic synthesis for ASICs
 IBM Journal of Research and Development
, 1996
"... Logic synthesis is the process of automatically generating optimized logic level representation from a highlevel description. With the rapid advances in integrated circuit technology and the resultant growth in design complexity, designers increasingly rely on logic synthesis to shorten the design ..."
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Cited by 14 (2 self)
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Logic synthesis is the process of automatically generating optimized logic level representation from a highlevel description. With the rapid advances in integrated circuit technology and the resultant growth in design complexity, designers increasingly rely on logic synthesis to shorten the design time, while achieving performance objectives. This paper describes the IBM logic synthesis system BooleDozer TM; including its organization, main algorithms and how it ts into the design process. The BooleDozer logic synthesis system has been widely used within IBM to successfully synthesize processor and ASIC designs. 1
Boolean Matching for Large Libraries
, 1998
"... Boolean matching tackles the problem whether a subcircuit of a boolean network can be substituted by a cell from a cell library. In previous approaches [7, 10, 8] each pair of a subcircuit and a cell is tested for NPN equivalence. This becomes very expensive if the cell library is large. In our appr ..."
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Cited by 11 (0 self)
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Boolean matching tackles the problem whether a subcircuit of a boolean network can be substituted by a cell from a cell library. In previous approaches [7, 10, 8] each pair of a subcircuit and a cell is tested for NPN equivalence. This becomes very expensive if the cell library is large. In our approach the time complexity for matching a subcircuit against a library L is almost independent of the size of L. CPU time also remains small for matching a subcircuit against the huge set of functions obtained by bridging and fixing cell inputs; but the use of these functions in technology mapping is very profitable. Our method is based on a canonical representative for each NPN equivalence class. We show how this representative can be computed efficiently and howitcanbe used for matching a boolean function against a set of library functions.
AreaOriented Synthesis for PassTransistor Logic
 in International Conference on Computer Design
, 1998
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