Deep submicron technology makes interconnect one of the main factors determining the circuit performance. Previous work shows that interconnect parameters exhibit a significant amount of spatial variation. In this work, we develop approaches to study the influence of the interconnect variation on circuit performance and to evaluate the circuit sensitivity to interconnect parameters. First, an accurate interconnect modeling technique is presented, and an interconnect model library is developed. Then, we explore an approach using parameterized interconnect models to study circuit sensitivity via a ring oscillator circuit. Finally, we present an alternative approach using statistical experimental design techniques to study the sensitivity of a large and complicated circuit to interconnect variations. Index Terms---Circuit analysis, interconnect, statistical analysis, worst case design. I. INTRODUCTION T HE CONTINUOUSLY increasing scale of integration used in the design and processing ...

Abstract—Computer-aided design (CAD) techniques are absolutely essential to harness the ever-increasing complexity of the microsystem design. Similarly, the technology CAD (TCAD) tools played a key role in the development of new technology generations. Although there is a common belief that the TCAD tools have been trailing the technology development, the situation has been changing very significantly especially over the last decade. For the deep submicrometer (DSM) devices, these tools provide a better insight than any measurement techniques and they have become indispensable in the new device creation. Moreover, these tools after calibration to a relatively small number of experiments, exhibit very impressive predictive power, which is utilized to speed up the technology integration and transfer to volume manufacturing. This results in very manufacturable high-yielding products that can be ramped up much faster than in the past decade, which is absolutely necessary given the huge costs of integrated circuit fabrication lines, short product lifecycles and penalties for being late to the market place. In this paper, we will present our perspective on the semiconductor technology development, and highlight the rapid growth of TCAD and its strategic use in semiconductor industry.

Abstract—In this paper, we present a methodology for simulating the impact of within-die (die-level) polysilicon critical dimension (poly-CD) variation on circuit performance. The methodology is illustrated on a 0.25 "m 642 8 SRAM macrocell layout. For this example, the impact as measured through signal skew is found to be significant and strongly dependent on the input address of the SRAM cell. I.

An interactive IC design methodology aimed at making designs less sensitive to manufacturing variations is presented, as well as a CAD tool to support it. The methodology, based on Taguchi's Robust Design Method, is shown to improve the performance and robustness of basic analog circuits. 1.0 Introduction The Robust Design Method is a technique aimed at designing high quality products at low cost. It is based on optimizing performance, manufacturability and cost by varying certain decision variables, in order to make the product less sensitive to manufacturing imperfections. Previously, IC variations were studied either in an ad hoc fashion or with a large number of simulations, which often led to long and expensive design cycles. Using a mathematical tool called orthogonal arrays, the Robust Design Method explores many variables in a small number of trials. The developed computer-aided design tool, DORIC (Design of Optimal & Robust Integrated Circuits) allows the user to study the e...

I hereby declare that I am the sole author of this thesis. This is a true copy of the thesis, including any required final revisions, as accepted by my examiners. I understand that my thesis may be made electronically available to the public. Derek Warren Wright ii Content addressable memories (CAMs) are gaining popularity with computer networks. Testing costs of CAMs are extremely high owing to their unique configuration. In this thesis, a fault analysis is carried out on an industrial ternary CAM (TCAM) design, and search path test algorithms are designed. The proposed algorithms are able to test the TCAM array, multiple-match resolver (MMR), and match address encoder (MAE). The tests represent a 6x decrease in test complexity compared to existing algorithms, while dramatically improving fault coverage. iii Acknowledgements First and foremost, I would like to thank my supervisor Dr. Manoj Sachdev for his guidance and support throughout my graduate studies. His kindness and generosity, along with his experience and expertise has pointed my life in a direction of research and continuous learning, for which I am grateful. I would also like to thank my CAM Group team members, Nitin Mohan and Wilson Fung, who are both very helpful, intelligent, and enjoyable to work with. Special thanks to Dr. Arokia Nathan and Dr. Andrew Kennings for reviewing this thesis. Their time, energy, and willingness to sit down and help me regardless of the task are greatly appreciated. Finally, I thank my family. Most people are not lucky enough to know someone as supportive, encouraging, and intelligent as my fiancée, Amy LeRoij, who truly is my lab partner for life. My parents and brother, who are continually supportive, and Amy’s parents, who treat me like one of their own, all deserve my true and sincere gratitude because they always have my best interests in mind. iv

This paper argues that the existing approaches to modeling and characterization of IC malfunctions are inadequate for test and yield learning of Deep Sub-Micron (DSM) products. Traditional notions of a spot defect and local and global process variations are analyzed and their shortcomings are exposed. A detailed taxonomy of process-induced deformations of DSM IC structures, enabling modeling and characterization of IC malfunctions, is proposed. The blueprint of a roadmap enabling such a characterization is suggested. Keywords: yield learning, fault modeling, defects, diagnosis, defect characterization. 1

Towards predictable deep-submicron manufacturing

Key characteristics of newly emerging IC technologies render the traditional concept of die size minimization and traditional "design rules" insufficient to handle the design-manufacturing interface. This tutorial surveys the design and process characteristics relevant to the manufacturability of submicron ICs. The discussion also covers analysis of design for manufacturability (DFM) tradeoffs. Yield and cost models needed to analyze these trade-offs are explained as well.