A formal and automatic verification of a real-life protocol is presented. The protocol, about 2800 lines of assembler code, has been used in products from the audio/video company Bang & Olufsen throughout more than a decade, and its purpose is to control the transmission of messages between audio/video components over a single bus. Such communications may collide, and one essential purpose of the protocol is to detect such collisions. The functioning is highly dependent on real-time considerations. Though the protocol was known to be faulty in that messages were lost occasionally, the protocol was too complicated in order for Bang & Olufsen to locate the bug using normal testing. However, using the real-time verification tool UPPAAL, an error trace was automatically generated, which caused the detection of "the error" in the implementation. The error was corrected and the correction was automatically proven correct, again using UPPAAL. A future, and more automated, version of the protocol, where this error is fatal, will incorporate the correction. Hence, this work is an elegant demonstration of how model checking has had an impact on practical software development. The effort of modeling this protocol has in addition generated a number of suggestions for enriching the UPPAAL language. Hence, it's also an excellent example of the reverse impact.

We study the complexity of restricted versions of s-t-connectivity, which is the standard complete problem for NL. In particular, we focus on different classes of planar graphs, of which grid graphs are an important special case. Our main results are: • Reachability in graphs of genus one is logspace-equivalent to reachability in grid graphs (and in particular it is logspace-equivalent to both reachability and non-reachability in planar graphs). • Many of the natural restrictions on grid-graph reachability (GGR) are equivalent under AC 0 reductions (for instance, undirected GGR, outdegree-one GGR, and indegree-one-outdegree-one GGR are all equivalent). These problems are all equivalent to the problem of determining whether a completed game position in HEX is a winning position, as well as to the problem of reachability in mazes studied by Blum and Kozen [BK78]. These problems provide natural examples of problems that are hard for NC 1 under AC 0 reductions but are not known to be hard for L; they thus give insight into the structure of L. • Reachability in layered planar graphs is logspace-equivalent to layered grid graph reachability (LGGR). We show that LGGR lies in UL (a subclass of NL). • Series-Parallel digraphs (on which reachability was shown to be decidable in logspace by Jakoby et al.) are a special case of single-source-single-sink planar directed acyclic graphs (DAGs); reachability for such graphs logspace reduces to single-source-single-sink acyclic grid graphs. We show that reachability on such grid graphs AC 0 reduces to undirected GGR. • We build on this to show that reachability for single-source multiple-sink planar DAGs is solvable in L. 1

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that the Boolean AND function can not be computed by polynomial size constant depth circuits built from modular counting gates, i.e., by CC 0 circuits. In this work we show that the AND function can be computed by uniform probabilistic CC 0 circuits that use only O(log n) random bits. This may be viewed as evidence contrary to the conjecture. As a consequence of our construction we get that all of ACC 0 can be computed by probabilistic CC 0 circuits that use only O(log n) random bits. Thus, if one were able to derandomize such circuits, we would obtain a collapse of circuit classes giving ACC 0 = CC 0. We present a derandomization of probabilistic CC 0 circuits using AND and OR gates to obtain ACC 0 = AND ◦ OR ◦ CC 0 = OR ◦ AND ◦ CC 0. AND and OR gates of sublinear fan-in suffice. Both these results hold for uniform as well as non-uniform circuit classes. For non-uniform circuits we obtain the stronger conclusion that ACC 0 = rand − ACC 0 = rand − CC 0 = rand(log n)−CC 0, i.e., probabilistic ACC 0 circuits can be simulated by probabilistic CC 0 circuits using only O(log n) random bits. As an application of our results we obtain a characterization of ACC 0 by constant width planar nondeterministic branching programs, improving a previous characterization for the quasipolynomial size setting. I.