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17
Optimal design of a CMOS opamp via geometric programming
 IEEE Transactions on ComputerAided Design
, 2001
"... We describe a new method for determining component values and transistor dimensions for CMOS operational ampli ers (opamps). We observe that a wide variety of design objectives and constraints have a special form, i.e., they are posynomial functions of the design variables. As a result the ampli er ..."
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Cited by 51 (10 self)
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We describe a new method for determining component values and transistor dimensions for CMOS operational ampli ers (opamps). We observe that a wide variety of design objectives and constraints have a special form, i.e., they are posynomial functions of the design variables. As a result the ampli er design problem can be expressed as a special form of optimization problem called geometric programming, for which very e cient global optimization methods have been developed. As a consequence we can e ciently determine globally optimal ampli er designs, or globally optimal tradeo s among competing performance measures such aspower, openloop gain, and bandwidth. Our method therefore yields completely automated synthesis of (globally) optimal CMOS ampli ers, directly from speci cations. In this paper we apply this method to a speci c, widely used operational ampli er architecture, showing in detail how to formulate the design problem as a geometric program. We compute globally optimal tradeo curves relating performance measures such as power dissipation, unitygain bandwidth, and openloop gain. We show how the method can be used to synthesize robust designs, i.e., designs guaranteed to meet the speci cations for a
A 13bit, 1.4MS/s SigmaDelta Modulator for RF Baseband Channel Applications
 IEEE J. SolidState Circuits
, 1998
"... modulator oversampling at 16 X is implemented in a 0.72 "m complementary metal–oxide–semiconductor process for use in the baseband path of a radiofrequency receiver. The modulator achieves 77 dB of dynamic range and dissipates 81 mW from a 3.3 V supply. It is characterized for the blocking and ..."
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Cited by 10 (1 self)
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modulator oversampling at 16 X is implemented in a 0.72 "m complementary metal–oxide–semiconductor process for use in the baseband path of a radiofrequency receiver. The modulator achieves 77 dB of dynamic range and dissipates 81 mW from a 3.3 V supply. It is characterized for the blocking and intermodulation requirements of a cordless telephone application. Index Terms—Analog–digital conversion, radio receivers, sampleddata circuits, sigma–delta modulation, switchedcapacitor circuits. I.
Activefeedback frequencycompensation technique for lowpower multistage amplifiers
 IEEE J. SolidState Circuits
, 2003
"... technique for lowpower operational amplifiers is presented in this paper. With an activefeedback mechanism, a highspeed block separates the lowfrequency highgain path and highfrequency signal path such that high gain and wide bandwidth can be achieved simultaneously in the AFFC amplifier. The ..."
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Cited by 7 (3 self)
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technique for lowpower operational amplifiers is presented in this paper. With an activefeedback mechanism, a highspeed block separates the lowfrequency highgain path and highfrequency signal path such that high gain and wide bandwidth can be achieved simultaneously in the AFFC amplifier. The gain stage in the activefeedback network also reduces the size of the compensation capacitors such that the overall chip area of the amplifier becomes smaller and the slew rate is improved. Furthermore, the presence of a lefthalfplane zero in the proposed AFFC topology improves the stability and settling behavior of the amplifier. Threestage amplifiers based on AFFC and nestedMiller compensation (NMC) techniques have been implemented by a commercial 0.8 m CMOS process. When driving a 120pF capacitive load, the AFFC amplifier achieves over 100dB dc gain, 4.5MHz gainbandwidth product (GBW) , 65 phase margin, and 1.5V / s average slew rate, while only dissipating 400 W power at a 2V supply. Compared to a threestage NMC amplifier, the proposed AFFC amplifier provides improvement in both the GBW and slew rate by 11 times and reduces the chip area by 2.3 times without significant increase in the power consumption. Index Terms—Active feedback, activecapacitivefeedback network, amplifiers, frequency compensation, multistage amplifiers.
A 0.9V 12mW 5MSPS algorithmic ADC with 77dB SFDR
 IEEE J. SolidState Circuits
, 2005
"... Abstract—An ultralowvoltage CMOS twostage algorithm ADC featuring high SFDR and efficient background calibration is presented. The adopted lowvoltage circuit technique achieves highaccuracy highspeed clocking without the use of clock boosting or bootstrapping. A resistorbased input sampling b ..."
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Cited by 5 (3 self)
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Abstract—An ultralowvoltage CMOS twostage algorithm ADC featuring high SFDR and efficient background calibration is presented. The adopted lowvoltage circuit technique achieves highaccuracy highspeed clocking without the use of clock boosting or bootstrapping. A resistorbased input sampling branch demonstrates high linearity and inherent lowvoltage operation. The proposed background calibration accounts for capacitor mismatches and finite opamp gain error in the MDAC stages via a novel digital correlation scheme involving a twochannel ADC architecture. The prototype ADC, fabricated in a 0.18 m CMOS process, achieves 77dB SFDR at 0.9 V and 5 MSPS (30 MHz clocking) after calibration. The measured SNR,
A CMOS LowDistortion Fully Differential Power Amplifier with Double Nested Miller Compensation
 IEEE J. SolidState Circuits
, 1993
"... Abstract—A fourstage fully differential power amplifier using a double nested Miller compensated structure is presented. The multipleloop configuration used results in a lower harmonic distortion, at least in the audio band, compared to conventional threestage amplifiers with nested Miller compen ..."
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Cited by 4 (0 self)
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Abstract—A fourstage fully differential power amplifier using a double nested Miller compensated structure is presented. The multipleloop configuration used results in a lower harmonic distortion, at least in the audio band, compared to conventional threestage amplifiers with nested Miller compensation. Design criteria and conditions for good stability of amplifiers using a multiple (greater than two) loop topology are presented. The amplifier operates with a single power supply which has a minimum value of 3 V. With a 5V supply, power dissipation is 10 mW and THD isS3 dB for a 6VP –P differential output signal at 10 kHz and a load of 50 Q. With 80 load and for a 10kHz, 4VP–P output signal, THD is68 dB. The chip area is 0.625 mm ’ in a 1.5~m singlepoly, doublemetal, nwell CMOS technology I.
Automatic synthesis of operational amplifiers based on analytic circuit models
 Proceedings of IEEE International Conference on ComputerAided Design
, 1987
"... An automatic synthesis tool for CMOS op amps (OPASYN) has been developed. The program starts from one of a number of op amp circuits and proceeds to optimize various device sizes and bias currents to meet a given set of design specifications. Because it uses analytic circuit models in its inner opti ..."
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Cited by 4 (0 self)
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An automatic synthesis tool for CMOS op amps (OPASYN) has been developed. The program starts from one of a number of op amp circuits and proceeds to optimize various device sizes and bias currents to meet a given set of design specifications. Because it uses analytic circuit models in its inner optimization loop, it can search efficiently through a large part of the possible solution space. The program has a SPICE interface that automatically performs circuit simulations for the candidate solutions to verify the results of the synthesis and optimization procedure. The simulation results are also used to finetune the analytic circuit descriptions in the database. OPASYN has been implemented in Franz Lisp and demonstrated for three different basic circuits with a conventional 3 µm process and a more advanced 1.5 µm process. Experiments have shown that OPASYN quickly produces practical designs which will meet reasonable design objectives. 1.
A 13.5b 1.2V micropower extended counting A/D converter
 IEEE J. SolidState Circuits
, 2001
"... Abstract—This work presents a study of the extended counting technique for a 1.2V micropower voiceband A/D converter. This extended counting technique is a blend of 61 modulation with its high resolution but relatively low speed and algorithmic conversion with its higher speed but lower accuracy. ..."
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Cited by 4 (1 self)
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Abstract—This work presents a study of the extended counting technique for a 1.2V micropower voiceband A/D converter. This extended counting technique is a blend of 61 modulation with its high resolution but relatively low speed and algorithmic conversion with its higher speed but lower accuracy. To achieve this, the converter successively operates first as a firstorder 61 modulator to convert the most significant bits, and then the same hardware is used as an algorithmic converter to convert the remaining least significant bits. An experimental prototype was designed in 0.8 m CMOS. With a 1.2V power supply, it consumes 150 W of power at a 16kHz Nyquist sampling frequency. The measured peak ƒ @x C „rhA was 80 dB and the dynamic range 82 dB. The converter core including the controller and all reconstruction logic occupies about I Q I mmP of chip area. This is considerably less than a complete 61 modulation A/D converter where the digital decimation filter would occupy a significant amount of chip area. Index Terms—Analogtodigital, extended counting, low power, low voltage. I.
Design of a high frequency low voltage CMOS operational amplifier
"... A method is presented in this paper for the design of a high frequency CMOS operational amplifier (OpAmp) which operates at 3V power supply using tsmc 0.18 micron CMOS technology. The OPAMP designed is a twostage CMOS OPAMP followed by an output buffer. This Operational Transconductance Amplifier ..."
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Cited by 1 (0 self)
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A method is presented in this paper for the design of a high frequency CMOS operational amplifier (OpAmp) which operates at 3V power supply using tsmc 0.18 micron CMOS technology. The OPAMP designed is a twostage CMOS OPAMP followed by an output buffer. This Operational Transconductance Amplifier (OTA) employs a Miller capacitor and is compensated with a current buffer compensation technique. The unique behaviour of the MOS transistors in saturation region not only allows a designer to work at a low voltage, but also at a high frequency. Designing of twostage opamps is a multidimensionaloptimization problem where optimization of one or more parameters may easily result into degradation of others. The OPAMP is designed to exhibit a unity gain frequency of 2.02GHz and exhibits a gain of 49.02dB with a 60.5 0 phase margin. As compared to the conventional approach, the proposed compensation method results in a higher unity gain frequency under the same load condition. Design has been carried out in Tanner tools. Simulation results are verified using Sedit and Wedit.
Programmable, HighDynamic Range SigmaDelta A/D Converter for Multistandard, FullyIntegrated CMOS RF Receiver
, 1998
"... A major focus of recent RF transceiver IC designs has been to increase both the integration and adaptability to multiple RF communication standards. Performing channel selection on chip at baseband allows the use of highintegration receiver architectures, and enhances programmability to different c ..."
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A major focus of recent RF transceiver IC designs has been to increase both the integration and adaptability to multiple RF communication standards. Performing channel selection on chip at baseband allows the use of highintegration receiver architectures, and enhances programmability to different channel bandwidths and dynamic range requirements of multiple RF standards. A wideband, highdynamic range sigmadelta modulator can be used to digitize both the desired signal and potentially stronger adjacentchannel interferers. In the digital domain, the decimation filter following the ADC can be easily made programmable. A 4thorder sigmadelta ADC which is capable of adapting to GSM (cellular) and DECT (cordless) communication standards is described. The ADC achieves 14 bits of resolution at 128x oversampling ratio (200kS/s Nyquist rate) for GSM, and 12 bits of i resolution at 32x oversampling ratio (1.4MS/s Nyquist rate) for DECT. Power reduction strategies are developed at both the sigmadelta architecture and circuit design levels. The experimental prototype, fabricated in a 0.35μm CMOS process, dissipates 70mW from a 3.3V supply.
A Design of Operational Amplifiers for Sigma Delta Modulators using 0.35um CMOS Process
"... : An operational amplifier designed with 0.35um CMOS technology is presented. All the transistors are realized with minimum or nearminimum channel length. As the short channel length causes performance degradation, a proper operational amplifier structure is selected to compensate the performance d ..."
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: An operational amplifier designed with 0.35um CMOS technology is presented. All the transistors are realized with minimum or nearminimum channel length. As the short channel length causes performance degradation, a proper operational amplifier structure is selected to compensate the performance degradation. The op amp is designed to meet the requirement of highspeed highresolution sigma delta modulators. It has a foldedcascode first stage and a classA output stage. It features a DC gain of 78dB, an openloop unitygain frequency of 266MHZ, a slew rate of 650V/us, and consumes 10.2mW from a +/1.5V power supply. High level simulation is used to evaluate the OTA performance in sigma delta modulators. 1. INTRODUCTION The fast development of CMOS process technique makes it possible to integrate more and more functions into a single DigitalsignalProcessing chip. However, the physical signal (which is analog) still needs an interface to be handled by DSP. A/D and D/A converters are...