Abstract—A 0.6-V 2-2 cascaded audio delta-sigma ADC is described. It uses a resistor-based sampling technique which achieves high linearity and low-voltage operation without subjecting the devices to large terminal voltages. A low-distortion feed-forward topology combined with nonlinear local feedback results in enhanced linearity by reducing the sensitivity to opamp distortion, and allows increased input amplitude, resulting in higher SNDR. The modulator achieves 82-dB dynamic range and 81-dB peak SNDR in the A-weighted audio signal bandwidth with an OSR of 64. The total power consumption of the modulator is 1 mW from a 0.6-V supply. The prototype occupies 2.9 mmP using a 0.35- m CMOS technology. Index Terms—Delta-sigma ADC, low voltage, switched-RC. I.

Abstract—The design of an ultra-low-voltage multistage (two-stage algorithmic) analog-to-digital converter (ADC) employing the opamp-reset switching technique is described. A highly linear input sampling circuit accommodates truly low-voltage sampling from external input signal source. A radix-based digital calibration technique is used to compensate for component mismatches and reduced opamp gain under low supply voltage. The radix-based scheme is based on a half-reference multiplying digital-to-analog converter structure, where the error sources seen by both the reference and input signal paths are made identical for a given stage. The prototype ADC was fabricated in a 0.18- m CMOS process. The prototype integrated circuit dissipates 9 mW at 0.9-V supply with an input signal range of 0.9 V differential. The calibration of the ADC improves the signal-to-noise-plus-distortion ratio from 40 to 55 dB and the spurious-free dynamic range from 47 to 75 dB. Index Terms—Analog-to-digital converter (ADC), digital calibration, input sampling circuit, opamp-reset switching, pseudodifferential, ultra-low voltage. I.

The implementation of active pixel based image sensors in CMOS technology is becoming increasingly important forproducing imaging systems that can be manufactured with low cost, low power, simple interface, and with good image quality. The major obstacle in the design of CMOS imagers is Fixed Pattern Noise (FPN) and Signal-to-Noise-Ratio (SNR) of the video output. This research focuses on minimizing FPN and improving SNR in linear CMOS image sensors which are needed in scanning and swiping applications such as nger print sensing, spectroscopy, and medical imaging systems. FPN is reduced in this research through the use of closed loop operational ampli ers in active pixels and through performing Correlated Double Sampling (CDS). SNR is improved by increasing the pixel saturation voltage. This thesis concludes that FPN can be reduced using the closed loop opamp bu ers. The major FPN noise sources are the shot noise from the photodiode, kTC noise from the sampling capacitors, and o set mismatches in the sample and hold ampli ers all of which are not compensated by CDS. Sample and hold ampli er o set mismatch is identi ed as

Abstract approved:

A 1.5-V, 10-bit, 14.3-MS/s pipeline analog-to-digital converter was implemented in a 0.6-m CMOS technology. Emphasis was placed on observing device reliability constraints at low voltage. MOS switches were implemented without lowthreshold devices by using a bootstrapping technique that does not subject the devices to large terminal voltages. The converter achieved a peak signal-to-noise-and-distortion ratio of 58.5 dB, maximum differential nonlinearity of 0.5 least significant bit (LSB), maximum integral nonlinearity of 0.7 LSB, and a power consumption of 36 mW. Index Terms---Analog to digital, low voltage, reliability. I. INTRODUCTION I N mixed-mode analog-to-digital (A/D) interfaces, there are many applications where a video-rate A/D converter (ADC) is integrated with complex digital signal-processing (DSP) blocks in a compatible, low-cost technology---particularly CMOS. Such applications include camcorders, wireless localarea -network transceivers, and digital set-top boxes. Ad...