this paper is organized as follows: Section 2 describes the architecture of the FAST-1 system and its key components. Section 3 discusses example implementations of two traffic scheduling algorithms in FAST-1. Section 4 compares the performance of the FAST testbed with conventional software simulation on a workstation. Finally, Section 5 concludes the paper with a summary of the current status and future directions for this research.

We develop a new class of asynchronous distributed algorithms for the explicit rate control of elastic sessions in an integrated packet network. Sessions can request for minimum guaranteed rate allocations (e.g., MCRs in the ATM context), and, under this constraint, we seek to allocate the max-min fair rates to the sessions. We capture the integrated network context by permitting the link bandwidths available to elastic sessions to be stochastically time varying. The available capacity of each link is viewed as some statistic of this stochastic process (e.g., a fraction of the mean, or a large deviations Equivalent Service Capacity (ESC)). For fixed available capacity at each link, we show that the vector of max-min fair rates can be computed from the root of a certain vector equation. A distributed asynchronous stochastic approximation technique is then used to develop a provably convergent distributed algorithm for obtaining the root of the equation, even when the link flows and the ...

this paper is organized as follows: Section II describes the architecture of the FAST system and its key components. Section III discusses an example implementation of a traffic scheduling algorithm based on weighted round-robin scheduling on the FAST-1 board and compares its performance with conventional software simulation on a workstation. Section IV concludes the paper with a summary of the current status and future directions for this research. 2 FAST-1 Architecture The first version of the testbed, called FAST-1, uses a printed-circuit board consisting of thirteen Altera FPGA devices as its building block. The board provides a total of 336,000 usable gates for implementing the simulation model of the target system, and up to 17 Mbytes of static RAM. The FAST-1 board is designed such that a single board can be used to simulate an Shared Memory EPF81500 EPF81500 EPF81500 EPF81500 EPF8050M EPF8050M EPF81500 Traffic Generator Traffic Generator Input Module Output Module Input Module Output Module 1 1 4 4 Interface Module Figure 1.1: Architecture of the FAST-1 board. ATM switch, and multiple boards can be interconnected via available connectors to simulate more complex switch fabrics or an entire ATM network consisting of multiple switches. The FPGAs allow implementation of the key simulations components in hardware. The testbed is currently interfaced through the ISA bus to a PC serving as the host system; however, since the interface logic of the testbed is implemented using programmable hardware, it can be interfaced to other busses by reprogramming the interface logic. Software tools control the programming of the FPGAs and the running of the simulations. Many different architectures for designing ATM switches have been proposed in the literature. These include s...

A significant portion of the traffic in packet data networks is from store-and-forward sessions. Such traffic flows are elastic, i.e., they can adapt to the transfer rate that the network can provide them. The network reserves bandwidth for real-time sessions, such as interactive voice, and dynamically shares the remaining bandwidth among the elastic sessions, in order to achieve some bandwidth sharing objective, such as max-min fairness. A distributed algorithm is required for this purpose. Several distributed algorithms for max-min fair rate allocation are available in the literature [9],[15], [16],[6]. The underlying assumption in these algorithms has been the availability of a fixed available capacity on each link for an extended period of time. However, in practice the available capacity will have rapid fluctuations due to the intrinsic rate variations of the guaranteed bandwidth flows. In this paper we develop an approach based on the distributed stochastic approximation algorith...

xi Acknowledgments xiii 1. Introduction 1 1.1 Traffic Scheduling in Input Buffered Switches : : : : : : : : : : : : : : : : : 6 1.2 Traffic Scheduling in Output Buffered Switches : : : : : : : : : : : : : : : : 9 1.2.1 Representative Schedulers : : : : : : : : : : : : : : : : : : : : : : : : 11 1.3 A Common Framework : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 17 1.3.1 End-to-End Delay Guarantees : : : : : : : : : : : : : : : : : : : : : 20 1.3.2 Fairness : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 21 1.3.3 Implementation Complexity : : : : : : : : : : : : : : : : : : : : : : : 23 1.4 Contributions : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 24 1.5 Dissertation Overview : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 27 2. Providing Bandwidth Guarantees in an Input-Buffered Switch 29 2.1 Weighted Probabilistic Iterative Matching : : : : : : : : : : : : : : : : : : : 33 2.2 Performance Evaluation : : : : : : : :...