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A Reconfigurable Hardware Approach to Network Simulation
 in ACM Transactions on Modeling and Simulation ' & $ % 50 Hardware Implementation of FairQueueing Algorithms
"... this paper is organized as follows: Section 2 describes the architecture of the FAST1 system and its key components. Section 3 discusses example implementations of two traffic scheduling algorithms in FAST1. Section 4 compares the performance of the FAST testbed with conventional software simulati ..."
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this paper is organized as follows: Section 2 describes the architecture of the FAST1 system and its key components. Section 3 discusses example implementations of two traffic scheduling algorithms in FAST1. Section 4 compares the performance of the FAST testbed with conventional software simulation on a workstation. Finally, Section 5 concludes the paper with a summary of the current status and future directions for this research.
A New Approach for Asynchronous Distributed Rate Control of Elastic Sessions in Integrated Packet Networks
 IEEE/ACM Trans. Networking
"... We develop a new class of asynchronous distributed algorithms for the explicit rate control of elastic sessions in an integrated packet network. Sessions can request for minimum guaranteed rate allocations (e.g., MCRs in the ATM context), and, under this constraint, we seek to allocate the maxmin f ..."
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We develop a new class of asynchronous distributed algorithms for the explicit rate control of elastic sessions in an integrated packet network. Sessions can request for minimum guaranteed rate allocations (e.g., MCRs in the ATM context), and, under this constraint, we seek to allocate the maxmin fair rates to the sessions. We capture the integrated network context by permitting the link bandwidths available to elastic sessions to be stochastically time varying. The available capacity of each link is viewed as some statistic of this stochastic process (e.g., a fraction of the mean, or a large deviations Equivalent Service Capacity (ESC)). For fixed available capacity at each link, we show that the vector of maxmin fair rates can be computed from the root of a certain vector equation. A distributed asynchronous stochastic approximation technique is then used to develop a provably convergent distributed algorithm for obtaining the root of the equation, even when the link flows and the ...
FAST: An FPGABased Simulation Testbed for ATM Networks
 in Proceedings of ICC'96
, 1996
"... this paper is organized as follows: Section II describes the architecture of the FAST system and its key components. Section III discusses an example implementation of a traffic scheduling algorithm based on weighted roundrobin scheduling on the FAST1 board and compares its performance with conven ..."
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Cited by 4 (2 self)
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this paper is organized as follows: Section II describes the architecture of the FAST system and its key components. Section III discusses an example implementation of a traffic scheduling algorithm based on weighted roundrobin scheduling on the FAST1 board and compares its performance with conventional software simulation on a workstation. Section IV concludes the paper with a summary of the current status and future directions for this research. 2 FAST1 Architecture The first version of the testbed, called FAST1, uses a printedcircuit board consisting of thirteen Altera FPGA devices as its building block. The board provides a total of 336,000 usable gates for implementing the simulation model of the target system, and up to 17 Mbytes of static RAM. The FAST1 board is designed such that a single board can be used to simulate an Shared Memory EPF81500 EPF81500 EPF81500 EPF81500 EPF8050M EPF8050M EPF81500 Traffic Generator Traffic Generator Input Module Output Module Input Module Output Module 1 1 4 4 Interface Module Figure 1.1: Architecture of the FAST1 board. ATM switch, and multiple boards can be interconnected via available connectors to simulate more complex switch fabrics or an entire ATM network consisting of multiple switches. The FPGAs allow implementation of the key simulations components in hardware. The testbed is currently interfaced through the ISA bus to a PC serving as the host system; however, since the interface logic of the testbed is implemented using programmable hardware, it can be interfaced to other busses by reprogramming the interface logic. Software tools control the programming of the FPGAs and the running of the simulations. Many different architectures for designing ATM switches have been proposed in the literature. These include s...
A distributed stochastic approximation approach for maxmin fair rate control of flows in packet networks
, 2006
"... We consider a distributed stochastic approximation algorithm that computes maxmin fair rate allocations to several elastic flows sharing a network (an elastic flow is one that can adapt its sending rate to the rate that the network can provide it). The flows are assumed to traverse a fixed sequence ..."
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Cited by 2 (0 self)
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We consider a distributed stochastic approximation algorithm that computes maxmin fair rate allocations to several elastic flows sharing a network (an elastic flow is one that can adapt its sending rate to the rate that the network can provide it). The flows are assumed to traverse a fixed sequence of links in the network. The available capacities at the network links are modeled as stochastic processes. Each session can request a minimum rate guarantee, hence we work with a notion of maxmin fairness with minimum rates. A major part of this paper is the proof that the rate allocation computed by the stochastic approximation iterations converges to maxmin rate. 1
Traffic Scheduling in PacketSwitched Networks: Analysis, Design, and Implementation
, 1996
"... xi Acknowledgments xiii 1. Introduction 1 1.1 Traffic Scheduling in Input Buffered Switches : : : : : : : : : : : : : : : : : 6 1.2 Traffic Scheduling in Output Buffered Switches : : : : : : : : : : : : : : : : 9 1.2.1 Representative Schedulers : : : : : : : : : : : : : : : : : : : : : : : : 11 1.3 ..."
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xi Acknowledgments xiii 1. Introduction 1 1.1 Traffic Scheduling in Input Buffered Switches : : : : : : : : : : : : : : : : : 6 1.2 Traffic Scheduling in Output Buffered Switches : : : : : : : : : : : : : : : : 9 1.2.1 Representative Schedulers : : : : : : : : : : : : : : : : : : : : : : : : 11 1.3 A Common Framework : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 17 1.3.1 EndtoEnd Delay Guarantees : : : : : : : : : : : : : : : : : : : : : 20 1.3.2 Fairness : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 21 1.3.3 Implementation Complexity : : : : : : : : : : : : : : : : : : : : : : : 23 1.4 Contributions : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 24 1.5 Dissertation Overview : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 27 2. Providing Bandwidth Guarantees in an InputBuffered Switch 29 2.1 Weighted Probabilistic Iterative Matching : : : : : : : : : : : : : : : : : : : 33 2.2 Performance Evaluation : : : : : : : :...