An integrated circuit that computes the velocity vector of a visual stimulus in one dimension is presented. The circuit combines optical sensors and associated electronics on a single silicon chip, processed with standard CMOS technology. The velocity is inferred from the time delay of the appearance of an image feature at two fixed locations on the chip. The circuit operates quite robustly for high-contrast stimuli over considerable irradiance and velocity ranges. With lower-contrast stimuli the output signal for a given velocity tends to decrease, while the direction selectivity is still maintained. The individual motion-sensing cells are compact, and they are therefore suited for use in dense 1D or 2D imaging arrays.

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This chapter covers device and circuit aspects of low-power analog CMOS circuit design. The fundamental limits constraining the design of low-power circuits are first recalled with an emphasis on the implications of supply voltage reduction. Biasing MOS transistors at very low current provides new features but requires dedicated models valid in all regions of operation including weak, moderate and strong inversion. Low-current biasing also has a strong influence on noise and matching properties. All these issues are discussed, together with the particular aspects related to passive devices and parasitic effects. The design process has to be supported by efficient and accurate circuit simulation. To this end, the EKV compact MOST model for circuit simulation is shortly presented. The use of the basic concepts such as pinch-off voltage, inversion factor and specific current are highlighted thanks to some very simple but fundamental circuits and to an effective use of the model. New design techniques that are appropriate for low-power and/or low-voltage circuits are presented with an emphasis on the analog floating point technique, the instantaneous companding principle, and their application to filters.

This paper describes CMOS circuits that generate a wideranging set of fixed bias currents, spanning at least 6 decades down to picoamperes. A master current generated by a bootstrapped current reference is successively divided by a current splitter to generate the desired references. An unpublished startup circuit and a novel power control mechanism are described. Measurements from a 0.35u implementation are presented and nonidealities are investigated. Readers are directed to a design kit that makes it simple to generate the layout for a bias generator with a set of desired currents for scalable MOSIS CMOS processes.

We describe a class of nonlinear circuits that accurately embody product-of-power-law relationships in the current signal domain. We call these circuits multiple-input translinear element (MITE) networks. A MITE is a circuit element that produces an output current that is exponenial in a weighted sum of its input voltages. We describe intuitively the basic operation of MITE networks and we show experimental data from a squaring-reciprocal circuit breadboarded from bipolar-- floating-gate MOS (biFGMOS) MITEs that we fabricated in a 2--m double-poly CMOS process available through MOSIS. 1. PRODUCT-OF-POWER-LAW CIRCUITS Products, quotients, and power-law relationships figure prominently in many signal and information processing algorithms. Consequently, analog circuits embodying such relaionships are important components in the construction of analog VLSI information processing systems. In the Nonlinear Circuits Handbook from Analog Devices, we find the following clear description of a ...

. This work studies the problem of CMOS operational amplifiers design optimisation. The synthesis of CMOS amplifiers can be translated into a multiple-objective optimisation task, in which a large number of specifications has to be taken into account, i.e., GBW, area, power consumption and others. We apply Genetic Algorithms [7] (GAs) to this problem; GAs are a computational optimisation technique which borrows some principles from biological evolution and have been widely applied to Computer Aided Design (CAD) of electronic circuits. A novel multi-objective optimisation methodology is embedded in our genetic algorithm and we focus mainly on the synthesis of micro-power analog cells. 1 Introduction We present a novel methodology applied to the problem of analog CMOS cells optimisation. Particularly, we tackle the issue of synthesising low-power operational amplifiers. The acquisition of micropower analog circuits is a major tendency in the electronics industry nowadays and, an...

We present analog VLSI neuromorphic architectures for a general class of learning tasks, which include supervised learning, reinforcement learning, and temporal di erence learning. The presented architectures are parallel, cellular, sparse in global interconnects, distributed in representation, and robust to noise and mismatches in the implementation. They use a parallel stochastic perturbation technique to estimate the e ect of weight changes on network outputs, rather than calculating derivatives based on a model of the network. This \model-free " technique avoids errors due to mismatchesinthephysical implementation of the network, and more generally allows to train networks of which the exact characteristics and structure are not known. With additional mechanisms of reinforcement learning, networks of fairly general structure are trained e ectively from an arbitrarily supplied reward signal. No prior assumptions are required on the structure of the network nor on the speci cs of the desired network response.

Synapses are a critical element of biologically-realistic, spike-based neural computation, serving the role of communication, computation, and modification. Many different circuit implementations of synapse function exist with different computational goals in mind. In this paper we describe a new CMOS synapse design that separately controls quiescent leak current, synaptic gain, and time-constant of decay. This circuit implements part of a commonly-used kinetic model of synaptic conductance.

Abstract—In this paper, we have identified a second-order reaction-diffusion differential equation able to reproduce through parameter setting different complex spatio-temporal behaviors. We have designed a log-domain hardware that implements the spatially discretized version of the selected reaction-diffusion equation. The logarithmic compression of the state variables allows several decades of variation of these state variables within subthreshold operation of the MOS transistors. Furthermore, as all the equation parameters are implemented as currents, they can be adjusted several decades. As a demonstrator, we have designed a chip containing a linear array of ten second-order dynamics coupled cells. Using this hardware, we have experimentally reproduced two complex spatio-temporal phenomena: the propagation of travelling waves and of trigger waves, as well as isolated oscillatory cells. Index Terms—Analog circuit design, analog very large scale integration (VLSI), current mode, logdomain, neural networks, nonlinear circuits, piecewise-linear circuit, subthreshold, weak inversion. I.

. Parameter variations cause unavoidable nonuniformities in Infra-Red Focal Plane Arrays and other integrated sensors. Since these nonuniformities change slowly with time, calibrating sensors one-time only is not suitable--much more frequent calibration is required. We have developed an algorithm that continually calibrates an array of sensors that contain gain and offset variations. This algorithm has been mapped to analog hardware and designed and fabricated with a 2um CMOS technology. Measured results from the chip show that the system achieves invariance to gain and offset variations of the input signal. Keywords: sensor calibration, nonuniformity correction, Infra-Red Focal Point Arrays 1. Introduction Transistor mismatches and parameter variations cause unavoidable nonuniformities in VLSI sensors. To counteract these variations between components, a one-time calibration procedure is normally used. Unfortunately, many of these variations fluctuate with time--either with operati...