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A 1.4V 10bit 25MS/s pipelined ADC using opampreset switching technique
 IEEE J. SolidSate Circuits
, 2003
"... Abstract—A lowvoltage opampreset switching technique (ORST) that does not use clock boosting, bootstrapping, switchedopamp (SO), or threshold voltage scaling is presented. This technique greatly reduces device reliability issues. Unlike the SO technique, the opamps stay active for all clock phase ..."
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Cited by 11 (3 self)
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Abstract—A lowvoltage opampreset switching technique (ORST) that does not use clock boosting, bootstrapping, switchedopamp (SO), or threshold voltage scaling is presented. This technique greatly reduces device reliability issues. Unlike the SO technique, the opamps stay active for all clock phases and, therefore, the ORST is suitable for highspeed applications. This new switching technique is applied to the design of a 10bit 25–MS/s pipelined analogtodigital converter (ADC). The prototype ADC was fabricated in a 0.35 m CMOS process and demonstrates 55dB signaltonoise ratio, 55dB spuriousfree dynamic range, and 48–dB signaltonoiseplusdistortion ratio performance with a 1.4V power supply. The total power consumption is 21 mW. The ADC’s minimum operating power supply is 1.3 V @ „r € aHW VA and the maximum operating frequency is 32 MS/s. The ORST is fully compatible with future lowvoltage submicron CMOS processes. Index Terms—Analogtodigital converter (ADC), low voltage, opampreset switching technique (ORST), pipeline. I.
A 0.6V 82dB deltasigma audio ADC using switchedRC integrators
 IEEE Journal of SolidState Circuits
, 2005
"... Abstract—A 0.6V 22 cascaded audio deltasigma ADC is described. It uses a resistorbased sampling technique which achieves high linearity and lowvoltage operation without subjecting the devices to large terminal voltages. A lowdistortion feedforward topology combined with nonlinear local feedba ..."
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Cited by 6 (1 self)
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Abstract—A 0.6V 22 cascaded audio deltasigma ADC is described. It uses a resistorbased sampling technique which achieves high linearity and lowvoltage operation without subjecting the devices to large terminal voltages. A lowdistortion feedforward topology combined with nonlinear local feedback results in enhanced linearity by reducing the sensitivity to opamp distortion, and allows increased input amplitude, resulting in higher SNDR. The modulator achieves 82dB dynamic range and 81dB peak SNDR in the Aweighted audio signal bandwidth with an OSR of 64. The total power consumption of the modulator is 1 mW from a 0.6V supply. The prototype occupies 2.9 mmP using a 0.35 m CMOS technology. Index Terms—Deltasigma ADC, low voltage, switchedRC. I.
Efficient CommonMode Feedback Circuits For PseudoDifferential
 in Proc. IEEE Int. Symp. Circuits and Systems
, 2000
"... Novel commonmode feedback circuits are proposed for use in pseudodifferential switchedcapacitor circuits. They can be implemented by incorporating just four additional capacitors (and switches) for an integrator, and only two additional capacitors for a residue gain amplifier. The circuits are ap ..."
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Cited by 5 (5 self)
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Novel commonmode feedback circuits are proposed for use in pseudodifferential switchedcapacitor circuits. They can be implemented by incorporating just four additional capacitors (and switches) for an integrator, and only two additional capacitors for a residue gain amplifier. The circuits are applicable to very lowvoltage switchedcapacitor stages realized in submicron lowvoltage CMOS processes.
A 0.9V 12mW 5MSPS algorithmic ADC with 77dB SFDR
 IEEE J. SolidState Circuits
, 2005
"... Abstract—An ultralowvoltage CMOS twostage algorithm ADC featuring high SFDR and efficient background calibration is presented. The adopted lowvoltage circuit technique achieves highaccuracy highspeed clocking without the use of clock boosting or bootstrapping. A resistorbased input sampling b ..."
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Cited by 5 (3 self)
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Abstract—An ultralowvoltage CMOS twostage algorithm ADC featuring high SFDR and efficient background calibration is presented. The adopted lowvoltage circuit technique achieves highaccuracy highspeed clocking without the use of clock boosting or bootstrapping. A resistorbased input sampling branch demonstrates high linearity and inherent lowvoltage operation. The proposed background calibration accounts for capacitor mismatches and finite opamp gain error in the MDAC stages via a novel digital correlation scheme involving a twochannel ADC architecture. The prototype ADC, fabricated in a 0.18 m CMOS process, achieves 77dB SFDR at 0.9 V and 5 MSPS (30 MHz clocking) after calibration. The measured SNR,
A 1V 10MHz clockrate 13bit CMOS 16 modulator using unitygainreset opamps
 IEEE J. SolidState Circuits
, 2002
"... Abstract—The problem of lowvoltage operation of switchedcapacitor circuits is discussed, and several solutions based on using unitygainreset of the opamps are proposed. Due to the feedback structure, the opamps do not need to be switched off during the reset phase of the operation, and hence can ..."
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Cited by 4 (4 self)
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Abstract—The problem of lowvoltage operation of switchedcapacitor circuits is discussed, and several solutions based on using unitygainreset of the opamps are proposed. Due to the feedback structure, the opamps do not need to be switched off during the reset phase of the operation, and hence can be clocked at a high rate. A lowvoltage 16 modulator, incorporating pseudodifferential unitygainreset opamps, is described. A test chip, realized in a 0.35 m CMOS process and clocked at 10.24 MHz, provided a dynamic range of 80 dB and a signaltonoise C distortion (SNDR) ratio of 78 dB for a 20kHz signal bandwidth, and a dynamic range of 74 dB and SNDR of 70 dB for a 50kHz bandwidth, with a 1V supply voltage. Index Terms—ADC, chargepump circuits, delta–sigma, low voltage, sigma–delta, switchedcapacitor circuits, switched opamp. I.
Sub1v design techniques for highlinearity multistage/pipelined analogtodigital converters
 IEEE Transactions on Circuits and SystemsI
, 2005
"... Abstract—The design of an ultralowvoltage multistage (twostage algorithmic) analogtodigital converter (ADC) employing the opampreset switching technique is described. A highly linear input sampling circuit accommodates truly lowvoltage sampling from external input signal source. A radixbased ..."
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Cited by 3 (2 self)
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Abstract—The design of an ultralowvoltage multistage (twostage algorithmic) analogtodigital converter (ADC) employing the opampreset switching technique is described. A highly linear input sampling circuit accommodates truly lowvoltage sampling from external input signal source. A radixbased digital calibration technique is used to compensate for component mismatches and reduced opamp gain under low supply voltage. The radixbased scheme is based on a halfreference multiplying digitaltoanalog converter structure, where the error sources seen by both the reference and input signal paths are made identical for a given stage. The prototype ADC was fabricated in a 0.18 m CMOS process. The prototype integrated circuit dissipates 9 mW at 0.9V supply with an input signal range of 0.9 V differential. The calibration of the ADC improves the signaltonoiseplusdistortion ratio from 40 to 55 dB and the spuriousfree dynamic range from 47 to 75 dB. Index Terms—Analogtodigital converter (ADC), digital calibration, input sampling circuit, opampreset switching, pseudodifferential, ultralow voltage. I.
Design Techniques for LowVoltage and LowPower AnalogtoDigital Converters
, 2005
"... Abstract approved: ..."
LowVoltage Pipelined Adc Using OpampReset Switching Technique
"... A lowvoltage opampreset switching technique (ORST) which avoids clock boosting/bootstrapping, switchedopamp, and threshold voltage scaling is presented. The switching technique is applied to the design of a 10bit 25MSPS pipelined ADC. The prototype ADC demonstrates 55dB SNR, 55dB SFDR, and 48dB ..."
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A lowvoltage opampreset switching technique (ORST) which avoids clock boosting/bootstrapping, switchedopamp, and threshold voltage scaling is presented. The switching technique is applied to the design of a 10bit 25MSPS pipelined ADC. The prototype ADC demonstrates 55dB SNR, 55dB SFDR, and 48dB SNDR at 1.4V power supply. The ADC operates down to 1.3V power supply (V TH,P =0.9V) with 5dB degradation in performance. Maximum operating frequency is 32MSPS. The ORST is fully compatible with future lowvoltage submicron CMOS processes.
IEEE 2007 Custom Intergrated Circuits Conference (CICC) A 1V 10b 30MSPS SwitchedRC Pipelined ADC
"... Abstract — A 10b 30MS/s pipelined ADC using fullydifferential switchedRC multiplying digitaltoanalog converter (MDAC) is presented. It utilizes a resistive loop to reset the feedback capacitor in the MDAC without using the �oating switch. The measured differential and integral nonlinearities of ..."
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Abstract — A 10b 30MS/s pipelined ADC using fullydifferential switchedRC multiplying digitaltoanalog converter (MDAC) is presented. It utilizes a resistive loop to reset the feedback capacitor in the MDAC without using the �oating switch. The measured differential and integral nonlinearities of the prototype IC fabricated in a 0.13µm CMOS process are less than 0.54 LSB and 1.75 LSB respectively. The prototype ADC achieves 51.6dB SNDR and 65.9dB SFDR with 1V supply while consuming 17mW power. I.
Design and Simulation of High Stability 2Stage Differential OpAmp Integrator in 180nm CMOS Technology
"... Abstract — Integrator is an OpAmp circuit application which does the mathematical operation of integration, i.e. the output voltage is proportional to the integral of input voltage. The stability of OpAmp circuit is analyzed by Gain and Phase Margin curves. This paper also discusses the power cons ..."
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Abstract — Integrator is an OpAmp circuit application which does the mathematical operation of integration, i.e. the output voltage is proportional to the integral of input voltage. The stability of OpAmp circuit is analyzed by Gain and Phase Margin curves. This paper also discusses the power consumption of OpAmp as well as Integrator analog circuit. The circuits are simulated and analyzed at 180nm standard CMOS process. The GainBandwidth product of Operational Amplifier is analyzed at different bias voltages. The power of Integrator is 7.844mW which is evaluated by using the OpAmp as the lower block of the Integrator. The Unity Gain Bandwidth of Operational Amplifier is 15 MHz at 0.7V biasing voltage and 21 MHz at 0.4V biasing voltage with power consumption of 7.158mW and 6.998mW, respectively.