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Automatic Synthesis of System on Chip Multiprocessor Architectures for Process Networks
- In Proc. Int. Conf. on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2004
, 2004
"... In this paper, we present an approach for automatic synthesis of System on Chip (SoC) multiprocessor architectures for applications expressed as process networks. Our approach is targeted towards design space exploration (DSE) and thus the speed of synthesis is of critical interest. The focus here i ..."
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Cited by 14 (2 self)
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In this paper, we present an approach for automatic synthesis of System on Chip (SoC) multiprocessor architectures for applications expressed as process networks. Our approach is targeted towards design space exploration (DSE) and thus the speed of synthesis is of critical interest. The focus here is on the problem of resource allocation and binding with a view to optimize cost under performance constraints. Our approach exploits adjacency relation of processes and uses a dynamic programming based algorithm to synthesize the architecture including interconnection network. We have done a number of experiments on real as well as randomly generated process networks. The results have been compared with an optimal MILP formulation. They conclusively show that this approach is fast as well as effective and can be employed for DSE.
Streamroller: Automatic synthesis of prescribed throughput accelerator pipelines
- In Proc. of the 4th International Conference on Hardware/Software Codesign and System Synthesis
, 2006
"... In this paper, we present a methodology for designing a pipeline of accelerators for an application. The application is modeled using sequential C language with simple stylizations. The synthesis of the accelerator pipeline involves designing loop accelerators for individual kernels, instantiating b ..."
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Cited by 9 (2 self)
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In this paper, we present a methodology for designing a pipeline of accelerators for an application. The application is modeled using sequential C language with simple stylizations. The synthesis of the accelerator pipeline involves designing loop accelerators for individual kernels, instantiating buffers for arrays used in the application, and hooking up these building blocks to form a pipeline. A compiler-based system automatically synthesizes loop accelerators for individual kernels at varying performance levels. An integer linear program formulation which simultaneously optimizes the cost of loop accelerators and the cost of memory buffers is proposed to compose the loop accelerators to form an accelerator pipeline for the whole application. Cases studies for some applications, including FMRadio and Beamformer, are presented to illustrate our design methodology. Experiments show significant cost savings are achieved through hardware sharing, while achieving the prescribed throughput requirements.
RPNG: A Tool for Random Process Network Generation
- In Proc. Asia and South Pacific International Conference in Embedded SoCs (ASPICES-2005), Banglore
, 2004
"... In this paper, we present a user controllable pseudo random process network generator (RPNG). It generates random process networks which can be used as test cases for tools related to application specific multiprocessor architectures. RPNG generates database of computation and communication attribut ..."
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Cited by 3 (2 self)
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In this paper, we present a user controllable pseudo random process network generator (RPNG). It generates random process networks which can be used as test cases for tools related to application specific multiprocessor architectures. RPNG generates database of computation and communication attributes of process networks for various processors and communication resources. These attributes are controlled by user specified parameters. RPNG also generates code for the process network ensuring that these networks are deadlock free. Generated code can be used as a workload either on a simulator or on an actual platform to study the underlying architecture. Another advantage of RPNG is that it enables one to reproduce results of other researchers.
Embedded system-level platform synthesis and application mapping for heterogeneous and hierarchical multiprocessor systems
, 2006
"... Copyright c©2006 by Wei Zhong, Leiden, The Netherlands. ..."
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Cited by 2 (0 self)
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Copyright c©2006 by Wei Zhong, Leiden, The Netherlands.
By Ashwani Kumar (2001416) Under the guidance of
"... the bonafide work carried out by them under my guidance and supervision at ..."
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the bonafide work carried out by them under my guidance and supervision at
RPNG: A Tool for Random Process Network Generation Basant Kumar Dwivedi Calypto Design Systems (I) Pvt. Ltd.
"... In this paper, we present a user controllable pseudo random process network generator (RPNG). It generates random process networks which can be used as test cases for tools related to application specific multiprocessor architectures. RPNG generates database of computation and communication attribut ..."
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In this paper, we present a user controllable pseudo random process network generator (RPNG). It generates random process networks which can be used as test cases for tools related to application specific multiprocessor architectures. RPNG generates database of computation and communication attributes of process networks for various processors and communication resources. These attributes are controlled by user specified parameters. RPNG also generates code for the process network ensuring that these networks are deadlock free. Generated code can be used as a workload either on a simulator or on an actual platform to study the underlying architecture. Another advantage of RPNG is that it enables one to reproduce results of other researchers. 1
