In this paper, we propose an optical communication structure for multiprocessor arrays which exploits the high communication bandwidth of optical waveguides. The structure takes advantage of two properties of optical signal transmissions on waveguides, namely unidirectional propagation and predictable propagation delays per unit length. Because of these two prop- erties, time-division multiplexing o1' messages has the same effect as message pipelining on optical waveguides. Two time-division multiplexing approaches are proposed and the combination of the two is used in the design of the optical communication structure. Analysis and simulation results are given to evaluate the communication effectiveness of the system. A clock distribution method is also proposed to address potential synchronization problems. Finally, feasibility issues with current and future technologies are discussed.

In this paper, time-division multiplexed multistage interconnection networks (TDM-MINs) are proposed for multiprocessor communications. Connections required by an application are partitioned into a number of subsets called mappings, such that connections in each mapping can be established in a MIN without conflict. Switch settings for establishing connections in each mapping are determined and stored in shift registers. By repeatedly changing switch settings, connections in each mapping are established for a time slot in a round-robin fashion. Thus, all connections required by an application may be established in a MIN in a time-division multiplexed way. TDM-MINs can emulate a completely connected network using N time slots. It can also emulate regular networks such as rings, meshes, Cube-Connected-Cycles (CCC), binary trees and n -dimensional hypercubes using 2, 4, 3, 4 and n time slots, respectively. The problem of partitioning an arbitrary set of requests into a minimal ...

Routing performance of optical interconnection networks is limited by both switch complexity and network connectivity. One way to overcome these limitations is to allocate the network bandwidth in a time-division multiplexed (TDM) fashion. With this technique, an appropriate subset of input-to-output connections can be established during a time slot and all possible connections can be established over several time slots. Emulating a fully connected network, however, requires a large multiplexing degree, and thus introduces latencies which may be prohibitive. As a solution, we propose a technique called Reconfiguration with Time Division Multiplexing (RTDM). With RTDM, only a subset, as required by applications, of all possible connections needs to be multiplexed in the network by letting the network go through a sequence of configurations. Network reconfiguration with TDM can be done either statically or dynamically. Static RTDM is applied when communication requirements of an applica...

In this paper we present deterministic algorithms for integer sorting and on-line packet routing on arrays with reconfigurable optical buses. The main objective is to identify the mechanisms specific to this type of architectures that allow us to build efficient integer sorting, partial permutation routing and h-relations algorithms. The consequences of these results on the PRAM simulation complexity are also investigated. Keywords: Optical pipelined buses, reconfigurable array, sorting, routing. 1. Introduction In large-scale general purpose parallel machines based on connection networks, efficient communication capabilities are essential in order to solve most of the problems of interest in a timely manner. Interprocessor communication networks are often the main bottlenecks in parallel machines. One important limitation of these networks concerns the exclusive access to the bus resources, which limits throughput to a function of the end-to-end propagation time. Optical communicati...

Computer architects have realized that interconnection bandwidth has become a critical limitation to the development of highperformance multiprocessor systems. Major reason is that the progress of processor performance has increasingly outpaced that of the interconnection networks, thereby limiting the usefulness of multiprocessor systems. This work presents a comprehensive study and the development of optoelectronic-based network routers. Optoelectronic technology can potentially provide ample bandwidth required by multiprocessor systems but at the same time can raise some critical issues that are discussed here such as on-chip wiring and chip packaging. We also proposed new architectural techniques suitable for the development of optoelectronic-based network routers to increase the network bandwidth utilization.

This paper presents an optical interconnect model for k-ary n-cube network topologies based on free-space analysis. This model integrates relevant parameters inherent to optics with traditional network parameters to make it applicable for performance evaluation of parallel processor optical network designs. We apply this model to a free-space diffractive-reflective optical interconnect design and compare our results with electronic-based networks.

Dedicated to my parents and brother

: We study the reduction of the internode communication latency in distributed-memory multiprocessor machines on the assumption of developing a new generation of optical busses. We consider quasi-transparent optical busses which convey optical packets in the asynchronous mode. The critical property of these busses is that the intranode latency is small compared to the internode propagation time so that the propagation of packets along the bus is determined by the sole velocity of light in the fibers. For 2D networks, this is just the contrary: the electronic node processing time generally controls the propagation of messages. We show that the optical bus outdoes several 2D electronic topologies both for the shortness of the latency and for the magnitude of the bandwidth. We briefly summarize in the last section the physical implementation of the optical bus and the structure of the bus/node interface. I. Introduction. The expression "distributed memory multiprocessor system" will be u...

: We present an investigation on how to reduce the internode communication latency in distributed multiprocessor systems. The strategy consists of replacing the "store and forward" mechanism that is usually carried out on each electronic node by a free diffusion of optical packets along an optical bus. No routing, no extraction of optical packets and no access arbitration into the bus are needed. Intermediate nodes between two processors engaged in a communication are optically transparent. These specifications considerably simplify the optoelectronic interface of the node and reduce the latency of communication. In the asynchronous operation mode that we consider, each node multiplexer inserts on the fly optical packets into the bus. The optical demultiplexer identifies the packet destination address before transmitting the data to the node electronics. The key point is to make the intranode latency shorter than the internode propagation time to attain a network latency close to ulti...

Optical interconnection technologies (OITs) are expected to play an important role in alleviating the technologically induced architectural and algorithmic compromises that have to be made in the design of high-performance, massively parallel processors (MPPs) and their target applications. The vast diversity and relative immaturity of the OITs that have been put forth, however, point to the need for a well-articulated strategy for their inclusion into the design methodology of these systems. In particular, a broad-based study that would categorize OITs according to those architectural and algorithmic paradigms they would most impact is required. To this end, this paper presents the structure of the Applications-Driven Optical Interconnect Technology (ADROIT) modeling framework and summarizes on-going work geared toward its full development. 1 Introduction During the last decade, interest in guided-wave and free-space optical interconnection technologies (OITs) for electronic paralle...