Computer architects have realized that interconnection bandwidth has become a critical limitation to the development of highperformance multiprocessor systems. Major reason is that the progress of processor performance has increasingly outpaced that of the interconnection networks, thereby limiting the usefulness of multiprocessor systems. This work presents a comprehensive study and the development of optoelectronic-based network routers. Optoelectronic technology can potentially provide ample bandwidth required by multiprocessor systems but at the same time can raise some critical issues that are discussed here such as on-chip wiring and chip packaging. We also proposed new architectural techniques suitable for the development of optoelectronic-based network routers to increase the network bandwidth utilization.

The WARRP router implements progressive deadlock recovery-based true-fully-adaptive routing in an efficient architecture designed to maximize flexibility as well as speed. The WARRP II version addresses the I/O pin-out problem by integrating dense high-bandwidth optoelectronic transceivers onto the router chip capable of providing over 300 GBytes/sec per square centimeter [7]. To our knowledge, this is the first fully-functional optoelectronic network router implemented to-date. 1 Introduction The importance of the interconnection network in highperformance parallel systems is conspicuous. The basic switching component that establishes the network's topology and determines the allowable paths packets can take through the network to guarantee deadlock freedom is the router. Previous network routers based on avoiding deadlock restrict routing freedom and do not efficiently utilize scarce network bandwidth, resulting in lower overall network performance and fault-tolerance capabilities....