This paper presents the architecture of a router designed to efficiently support traffic generated by multimedia applications. The router is targeted for use in clusters and LANs rather than in WANs, the latter being served by communication substrates such as ATM. The distinguishing features of the proposed router architecture are the use of small fixed-size buffers, a large number of virtual channels, linklevel virtual channel flow control, support for dynamic modification of connection bandwidth and priorities, and coordinated scheduling of connections across all output channels. The paper begins with a discussion of the design choices and architectural trade-offs made in the current MultiMedia Router (MMR) project. The performance evaluation section presents some preliminary results of the coordinated scheduling of constant bit rate (CBR) traffic streams. 1.0 Introduction In the past few years we have seen an explosive growth in network-based multimedia application...

this paper. With much lower VLSI costs than adaptive wormhole routers, the adaptive Bubble router is even faster than deterministic wormhole routers based on virtual channels. This has been achieved by combining a low-cost deadlock avoidance mechanism for virtual cut-through networks, called Bubble flow control, with an adequate design of the router's arbiter

A router design for torus networks that significantly reduces message latency over traditional wormhole routers is presented in this paper. This new router implements virtual cut-through switching and fully-adaptive minimal routing. Packet deadlock is avoided by providing escape ways governed by Bubble flow control, a mechanism that guarantees enough free buffer space in the network to allow continuous packet movement.

Computer architects have realized that interconnection bandwidth has become a critical limitation to the development of highperformance multiprocessor systems. Major reason is that the progress of processor performance has increasingly outpaced that of the interconnection networks, thereby limiting the usefulness of multiprocessor systems. This work presents a comprehensive study and the development of optoelectronic-based network routers. Optoelectronic technology can potentially provide ample bandwidth required by multiprocessor systems but at the same time can raise some critical issues that are discussed here such as on-chip wiring and chip packaging. We also proposed new architectural techniques suitable for the development of optoelectronic-based network routers to increase the network bandwidth utilization.

k-ary m-way networks are multi-dimensional mesh and tori networks based on m-way channels. An m-way channel is the physical wiring of m links. An m-way router interfaces two m-way channels only, irrespective of the network topology or dimension. This has important advantages: the same router can be used to build networks of various dimensionalities and topologies; physical channels can have very wide data links; and broadcasting and multicasting are facilitated. The design of a switch-free mway channel wormhole router is detailed in this paper. Channel arbitration, buffer management, and routing are presented. The performance of k-ary m-way networks is evaluated. Keywords: m-way channel, k-ary m-way network, m-way router architecture, performance evaluation. 1 Introduction Direct interconnection networks use direct links between routers. A physical bi-directional link connecting two routers in a k-ary n-cube network can be implemented either as one set of bi-directional wires called...