Itiswell-knownthatmemorylatency,energy, capacity,bandwidth, and scalability will be critical bottlenecks in future large-scale systems. This paper addresses these problems, focusing on the interface between the compute cores and memory, comprising the physical interconnect and the memory access protocol. For the physical interconnect, we study the prudent use of emerging silicon-photonic technology to reduce energy consumption and improve capacity scaling. We conclude that photonics are effective primarily to improve socket-edge bandwidth by breaking the pin barrier, and for use on heavily utilized links. For the access protocol, we propose a novel packet based interface that relinquishes most of the tight control that the memory controller holds in current systems and allows the memory modules to be more autonomous, improving flexibility and interoperability. The key enabler here is the introduction of a 3Dstacked interface die that allows both these optimizations without modifying commodity memory dies. The interface die handles all conversion between optics and electronics, as well as all low-level memory device control functionality. Communication beyond the interface die is fully electrical, with TSVs between dies and low-swing wires on-die. We show that such an approach results in substantially lowered energy consumption, reduced latency, better scalability to large capacities, and better support for heterogeneity and interoperability.

Low-power and electrically controlled optical sources are vital for next generation optical interconnect systems to meet strict energy demands. Current optical transmitters consisting of high-threshold lasers plus external modulators consume far too much power to be competitive with future electrical interconnects. Here we demonstrate a directly modulated photonic crystal nanocavity light-emitting diode (LED) with 10 GHz modulation speed and less than 1 fJ per bit energy of operation, which is orders of magnitude lower than previous solutions. The device is electrically controlled and operates at room temperature, while the high modulation speed results from the fast relaxation of the quantum dots used as the active material. By virtue of possessing a small mode volume, our LED is intrinsically single mode and, therefore, useful for communicating information over a single narrowband channel. The demonstrated device is a major step forward in providing practical low-power and integrable sources for on-chip photonics.

Abstract — State-of-the-art System-on-Chip (SoC) consists of hundreds of processing elements, while trends in design of the next generation of SoC point to integration of thousand of processing elements, requiring high performance interconnect for high throughput communications. Optical on-chip interconnects are currently considered as one of the most promising paradigms for the design of such next generation Multi-Processors System on Chip (MPSoC). They enable significantly increased bandwidth, increased immunity to electromagnetic noise, decreased latency, and decreased power. Therefore, defining new architectures taking advantage of optical interconnects represents today a key issue for MPSoC designers. Moreover, new design methodologies, considering the design constraints specific to these architectures are mandatory. In this paper, we present a contention-free new architecture based on optical network on chip, called Optical Ring Network-on-Chip (ORNoC). We also show that our network scales well with both large 2D and 3D architectures. For the efficient design, we propose automatic wavelength-/waveguide assignment and demonstrate that the proposed architecture is capable of connecting 1296 nodes with only 102 waveguides and 64 wavelengths per waveguide. I.

Ultralow-threshold electrically pumped quantumdot

crystal cavities yield low-power optoelectronic devices

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Abstract—Trends in design of the next generation of Multi-Processors System on Chip (MPSoC) point to 3D integration of thousand of processing elements, requiring high performance interconnect for high throughput and low latency communications. Optical on-chip interconnects enable significantly increased bandwidth and decreased latency. They are thus considered as one of the most promising paradigms for the design of such system. However, existence of interfaces between electronic and photonic signals implies strong constraints on the layout of the 3D architecture and may impact the architecture scalability. In this paper, we propose and evaluate a possible layout for an optical Network-on-Chip used to interconnect processing elements located on different electrical layers. I.

In this paper we examine the question of when and whether to use photonic interconnects from a computer architect’s perspective. Specifically we show that since electronics and photonic devices scale differently, the electrical transport network and the utilization of a link play crucial roles in determining the energy efficiency of a link. Consequently there is a limit to the amount of bandwidth photonic links can deliver with the maximum energy efficiency, so picking the target bandwidth is a crucial decision in a future multicore processor. Furthermore, it means that maximizing the number of wavelengths in a waveguide need not be a priority for device researchers. We also show that when link utilization is taken into account the cross-over point between when photonic and electronic links are more efficient might be lower than what was previously considered. 1.