this article the second representation mentioned above. We first recall the main properties of computable real numbers. We deduce from one definition, among the three definitions of this notion, a representation of these numbers as sequence of finite B-adic numbers and then we describe algorithms for rational operations and transcendental functions for this representation. Finally we describe briefly the prototype written in Caml. 2. Computable real numbers

A very fast Jacobi-like algorithm for the parallel solution of symmetric eigenvalue problems is proposed. It becomes possible by not focusing on the realization of the Jacobi rotation with a CORDIC processor, but by applying approximate rotations and adjusting them to single steps of the CORDIC algorithm, i.e., only one angle of the CORDIC angle sequence defines the Jacobi rotation in each step. This angle can be determined by some shift, add and compare operations. Although mly linear convergence is obtained for the most simple version of the new algorithm, the overall operation count (shifts and adds) decreases dramatically. A slow increase of the number of involved CORDIC angles during the runtime retains quadratic convergence.

Traditionally, CORDIC algorithms have employed radix-2 in the first n/2 microrotations (n is the precision in bits) in order to preserve a constant scale factor. In this work we will present a full radix-4 CORDIC algorithm in rotation mode and circular coordinates and its corresponding selection function, and we will propose an efficient technique for the compensation of the non constant scale factor. Three radix-4 CORDIC architectures are implemented: a) a word serial architecture based on the zero skipping technique; b) a pipelined architecture; and c) an application specific architecture (the angles are known beforehand). The first two are general purpose implementations in redundant arithmetic (carry-save), whereas the last one is a simplification of the first two. The proposed architectures are time and/or area efficient when compared with already existing CORDIC architectures. 1. Introduction The CORDIC (COordinate Rotation DIgital Computer) algorithm was introduced by Volder [...

This is the second part of a study which deals with the design of an application specific architecture for fast orthogonal transforms based on the successive doubling method. In this work we will analyze six of the most important fast transforms: Complex Valued Fourier (CFFT), Walsh (FWT), Hartley (FHT), Real Valued Fourier (RFFT), Cosine (FCT), and Haar (FHrT). Out of them, only the CFFT and the FWT posses a data flow coinciding with the one generated by the successive doubling method. The other four require some type of hardware modification to guarantee the constant geometry of the successive doubling method. The FHT and the RFFT require that the radix r butterflies (N = r n , N is the length of the input sequence and n the number of stages of the transform) be processed as pairs and the data flow must be corrected when the transformation angle is not zero. The FCT, which we compute using an indirect method (n + 1 stages) based on the FHT, requires that the two first stages be eva...

This paper presents a novel CORDIC algorithm and architecture for the rotation and vectoring mode in circular coordinate systems in which the directions of all micro-rotations are precomputed while maintaining a constant scale factor. Thus, an examination of the sign of the angle or y-remainder after each iteration is no longer required. By using Most-Significant Digit (MSD) first adder/multiplier, the critical path of the entire CORDIC architecture only requires (1:5n + 2) and (1:5n + 10) full-adders (n corresponds to the word-length of the inputs) for rotation and vectoring modes, respectively. This is a speed improvement of about 30% compared to the previously fastest reported shared rotation and vectoring mode implementations. Additionally, there is a higher degree of freedom in choosing the pipeline cutsets due to the novel independence of iteration i and i-1 in the CORDIC rotation. Optional pipelining can lead for example to an on-line delay of three clock-cycles where every cloc...

This paper describes PSEUDEC, a dedicated co-processor and the rationale behind it's design. The final goal of our work is to present a single chip solution with low power consumption for an advanced digital hearing aid based on a parameterized transformation of speech (PARTRAN). Characterization of the constituent parts of the PARTRAN algorithm shows, that it is well suited for implementation on a heterogeneous architecture. The design strategy used identifies a subset suited for implementation on dedicated hardware, with computational complexity roughly equivalent to the performance of a standard 10 MIPS DSP. The subset of PARTRAN implemented by PSEUDEC performs PSEUdo DEComposition of a 12th order LPC polynomial. An adapted algorithm displays improved dynamic range compared to a conventional solution suited for DSP's, calculating the amplitude spectrum rather than the power spectrum. Highly pipelined CORDIC-units optimized for the application replaces complex multiplication, trigono...

The compensation of scale factor imposes significant computation overhead on the CORDIC algorithm. In this paper we present two algorithms and the corresponding architectures (one for both rotation and vectoring modes and the other only for rotation mode) to perform the scaling factor compensation in parallel with the classical CORDIC iterations. With these methods, the scale factor compensation overhead is reduced to a couple of iterations for any word length. The architectures presented have been optimized for conventional and redundant arithmetic. 1 Introduction The CORDIC algorithm (COordinate Rotation DIgital Computer) was introduced to compute trigonometric functions and generalized to compute linear and hyperbolic functions [Vol59][Wal71]. It is an iterative algorithm suitable for VLSI implementation because it employs only adders and shifters and it has a wide application field. Special attention has been paid by different researchers to the improvement of the algorithm in the...

This report consider the generalised CORDIC algorithm from a theoretical point of view, involving principles, applications and range of convergence. Further is considered the derivation of an instance of this algorithm, allowing computations in circular and linear modes, denoted LCC. Since LCC is intended for use as a BCU in an ASIC VLSI implementation of the DITPOS algorithm, the specifications for LCC has been derived from this application, although it may find application in other designs as well, provided the numerical needs match the one offered by LCC. Also, the derivation of a highly pipelined array architecture with high resource utilisation is treated in detail. The architecture is based upon bit-serial arithmetic, and a physical implementation of a prototype for this architecture is included. The implementation is based on the SOLO 1400 standard cell tool. Table of Contents 1 Introduction 1 2 Theoretical background 2 2.1 Planar Rotations and their computation using CORDI...

this paper. By introducing an extra termination symbol, which signals that an operand was merely terminated due to its length exceeding some bound, operands can be kept as intervals, representing an imprecise operand. Operands terminated in the ordinary way can be taken to represent exact numbers. The cube modeling a function of two variables, can be generalized to a hypercube modeling a poly-homographic function of n variables. For n = 3 the function is defined as:

We propose a CORDIC–like algorithm for computing the feed–forward phase of a Support Vector Machine (SVM) in fixed–point arithmetic, using only shift and add operations and avoiding resource–consuming multiplications. This result is obtained thanks to a hardware–friendly kernel, which greatly simplifies the SVM feed–forward phase computation and, at the same time, maintains good classification performance respect to the conventional gaussian kernel.