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22
Arbitrary Precision Real Arithmetic: Design and Algorithms
, 1996
"... this article the second representation mentioned above. We first recall the main properties of computable real numbers. We deduce from one definition, among the three definitions of this notion, a representation of these numbers as sequence of finite Badic numbers and then we describe algorithms fo ..."
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this article the second representation mentioned above. We first recall the main properties of computable real numbers. We deduce from one definition, among the three definitions of this notion, a representation of these numbers as sequence of finite Badic numbers and then we describe algorithms for rational operations and transcendental functions for this representation. Finally we describe briefly the prototype written in Caml. 2. Computable real numbers
An efcient Jacobilike algorithm for parallel eigenvalue computation
 IEEE Trans. of Comp
, 1993
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High performance rotation architectures based on the radix4 CORDIC algorithm
 IEEE Transactions on Computers
, 1997
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PCORDIC: A Precomputation Based Rotation CORDIC Algorithm
 EURASIP JOURNAL ON APPLIED SIGNAL PROCESSING 2002:9, 936–943
, 2002
"... This paper presents a CORDIC (coordinate rotation digital computer) algorithm and architecture for the rotation mode in which the directions of all microrotations are precomputed while maintaining a constant scale factor. Thus, an examination of the sign of the angle after each iteration is no long ..."
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This paper presents a CORDIC (coordinate rotation digital computer) algorithm and architecture for the rotation mode in which the directions of all microrotations are precomputed while maintaining a constant scale factor. Thus, an examination of the sign of the angle after each iteration is no longer required. The algorithm is capable to perform the CORDIC computation for an operand wordlength of 54 bits. Additionally, there is a higher degree of freedom in choosing the pipeline cutsets due to the novel feature of independence of the iterations i and i − 1 in the CORDIC rotation.
A HighSpeed CORDIC Algorithm and Architecture for DSP Applications
 in Proc. of the 1999 IEEE Workshop on Signal Processing Systems (SiPS’99
, 1999
"... This paper presents a novel CORDIC algorithm and architecture for the rotation and vectoring mode in circular coordinate systems in which the directions of all microrotations are precomputed while maintaining a constant scale factor. Thus, an examination of the sign of the angle or yremainder afte ..."
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Cited by 4 (3 self)
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This paper presents a novel CORDIC algorithm and architecture for the rotation and vectoring mode in circular coordinate systems in which the directions of all microrotations are precomputed while maintaining a constant scale factor. Thus, an examination of the sign of the angle or yremainder after each iteration is no longer required. By using MostSignificant Digit (MSD) first adder/multiplier, the critical path of the entire CORDIC architecture only requires (1:5n + 2) and (1:5n + 10) fulladders (n corresponds to the wordlength of the inputs) for rotation and vectoring modes, respectively. This is a speed improvement of about 30% compared to the previously fastest reported shared rotation and vectoring mode implementations. Additionally, there is a higher degree of freedom in choosing the pipeline cutsets due to the novel independence of iteration i and i1 in the CORDIC rotation. Optional pipelining can lead for example to an online delay of three clockcycles where every cloc...
Parallel Compensation of Scale Factor for the CORDIC Algorithm
 IN PRESS IN VLSI OF SIGNAL PROCESSING
, 1998
"... The compensation of scale factor imposes significant computation overhead on the CORDIC algorithm. In this paper we present two algorithms and the corresponding architectures (one for both rotation and vectoring modes and the other only for rotation mode) to perform the scaling factor compensation i ..."
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Cited by 4 (1 self)
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The compensation of scale factor imposes significant computation overhead on the CORDIC algorithm. In this paper we present two algorithms and the corresponding architectures (one for both rotation and vectoring modes and the other only for rotation mode) to perform the scaling factor compensation in parallel with the classical CORDIC iterations. With these methods, the scale factor compensation overhead is reduced to a couple of iterations for any word length. The architectures presented have been optimized for conventional and redundant arithmetic.
Feedforward Support Vector Machine Without Multipliers
, 2006
"... We propose a CORDIC–like algorithm for computing the feed–forward phase of a Support Vector Machine (SVM) in fixed–point arithmetic, using only shift and add operations and avoiding resource–consuming multiplications. This result is obtained thanks to a hardware–friendly kernel, which greatly simpli ..."
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Cited by 3 (0 self)
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We propose a CORDIC–like algorithm for computing the feed–forward phase of a Support Vector Machine (SVM) in fixed–point arithmetic, using only shift and add operations and avoiding resource–consuming multiplications. This result is obtained thanks to a hardware–friendly kernel, which greatly simplifies the SVM feed–forward phase computation and, at the same time, maintains good classification performance respect to the conventional gaussian kernel.
ApplicationSpecific Architecture For Fast Transforms Based On The Successive Doubling Method, Part II: Orthogonal Transforms
, 1994
"... This is the second part of a study which deals with the design of an application specific architecture for fast orthogonal transforms based on the successive doubling method. In this work we will analyze six of the most important fast transforms: Complex Valued Fourier (CFFT), Walsh (FWT), Hartley ( ..."
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This is the second part of a study which deals with the design of an application specific architecture for fast orthogonal transforms based on the successive doubling method. In this work we will analyze six of the most important fast transforms: Complex Valued Fourier (CFFT), Walsh (FWT), Hartley (FHT), Real Valued Fourier (RFFT), Cosine (FCT), and Haar (FHrT). Out of them, only the CFFT and the FWT posses a data flow coinciding with the one generated by the successive doubling method. The other four require some type of hardware modification to guarantee the constant geometry of the successive doubling method. The FHT and the RFFT require that the radix r butterflies (N = r n , N is the length of the input sequence and n the number of stages of the transform) be processed as pairs and the data flow must be corrected when the transformation angle is not zero. The FCT, which we compute using an indirect method (n + 1 stages) based on the FHT, requires that the two first stages be eva...
CORDIC Algorithms and Architectures
"... Digital signal processing (DSP) algorithms exhibit an increasing need for the efficient implementation of complex arithmetic operations. The computation of trigonometric functions, coordinate transformations or rotations of complex valued phasors is almost naturally involved with modern DSP algorith ..."
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Cited by 2 (0 self)
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Digital signal processing (DSP) algorithms exhibit an increasing need for the efficient implementation of complex arithmetic operations. The computation of trigonometric functions, coordinate transformations or rotations of complex valued phasors is almost naturally involved with modern DSP algorithms. Popular application examples are algorithms used in digital communication technology and in adaptive signal processing. While in digital communications, the straightforward evaluation of the cited functions is important, numerous matrix based adaptive signal processing algorithms require the solution of systems of linear equations, QR factorization or the computation of eigenvalues, eigenvectors or singular values. All these tasks can be e ciently implemented using processing elements performing vector rotations. The COordinate Rotation DIgital Computer algorithm (CORDIC) o ers the opportunity to calculate all the desired functions in a rather simple and elegant way. The CORDIC algorithm was rst introduced byVolder [1] for the computation
Radix4 vectoring CORDIC algorithm and architectures
, 1998
"... In this work we extend the radix4 CORDIC algorithm to the vectoring mode (the radix4 CORDIC algorithm was proposed recently by the authors for the rotation mode). The extension to the vectoring mode is not straightforward, since the digit selection function is more complex in the vectoring case t ..."
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Cited by 2 (2 self)
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In this work we extend the radix4 CORDIC algorithm to the vectoring mode (the radix4 CORDIC algorithm was proposed recently by the authors for the rotation mode). The extension to the vectoring mode is not straightforward, since the digit selection function is more complex in the vectoring case than in the rotation case; as in the rotation mode, the scale factor is not constant. Although the radix4 CORDIC algorithm in vectoring mode has a similar recurrence as the radix4 division algorithm, there are specific issues concerning the vectoring algorithm that demand dedicated study. We present the digit selection for nonredundant and redundant arithmetic (following two different approaches: arithmetic comparisons and table lookup), the computation and compensation of the scale factor, and the implementation of the algorithm (with both types of digit selection) in a wordserial architecture. When compared with conventional radix2 (redundant and nonredundant) architectures, th...