A skip and fill algorithm is developed to digitally self-calibrate pipelined analog-to-digital converters (ADC's) in real time. The proposed digital calibration technique is applicable to capacitor-ratioed multiplying digital-to-analog converters (MDAC's) commonly used in multi-step or pipelined ADC's. This background calibration process can replace, in effect, a trimming procedure usually done in the factory with a hidden electronic calibration. Unlike other self-calibration techniques working in the foreground, the proposed technique is based on the concept of skipping conversion cycles randomly but filling in data later by nonlinear interpolation. This opens up the feasibility of digitally implementing calibration hardware and simplifying the task of self-calibrating multi-step or pipelined ADC's. The proposed method improves the performance of the inherently fast ADC's by maintaining simple system architectures. To measure errors resulting from capacitor mismatch, op amp dc gain, offset, and switch feedthrough in real time, the calibration test signal is injected in place of the input signal using a split-reference injection technique. Ultimately, the missing signal within 2/3 of the Nyquist bandwidth is recovered with 16-bit accuracy using a 44-th order polynomial interpolation, behaving essentially as an FIR filter.

The architecture, implementation, and applications of a special purpose neural network processor are described. The chip performs over 2000 multiplications and additions simultaneously. Its datapath is particularly suitable for the convolutional topologies that are typical in classification networks, but can also be configured for fully connected or feedback topologies. Resources can be multiplexed to permit implementation of networks with several hundreds of thousands of connections on a single chip. Computations are performed with 6 Bits accuracy for the weights and 3 Bits for the neuron states. Analog processing is used internally for reduced power dissipation and higher density, but all input/output is digital to simplify system integration. The practicality of the chip is demonstrated with an implementation of a neural network for optical character recognition. This network contains over 130,000 connections and is evaluated in 1 ms.

This paper describes a background calibration method for enhancing the accuracy and linearity of a switched-capacitor digital-to-analog converter. It can be used alone or in combination with mismatch shaping to achieve very high accuracy and linearity combined with high speed. 1.

Automatic Synthesis of CMOS Digital/Analog Converters by Robert McKinstry Robinson Neff Doctor of Philosophy in Engineering -- Electrical Engineering and Computer Sciences University of California at Berkeley Professor Paul R. Gray, Chair Synthesis of analog functional blocks in integrated circuits offers promise for improved designer productivity. By developing module generators for commonly used analog circuit elements, a synthesis methodology may be matched to a particular application, with approaches and algorithms determined by the particular needs of target circuit type. An analog circuit designer should be able to input design specifications and underlying technology information, and a synthesis methodology should determine circuit parameter values and dimensions, creating the required mask layouts. Slow, tedious design and redesign methods should be replaced by one in which the computer finds minimum cost designs which meet performance requirements. This work implements synthesis methods for a widely used analog block, the digital/analog converter (DAC).

Abstract — A 14-bit digital-to-analog converter based on a fourth-order multibit sigma–delta modulator is described. The digital modulator is pipelined to minimize both its power dissipation and design complexity. The 6-bit output of this modulator is converted to analog using 64 current-steering cells that are continuously calibrated to a reference current. This converter achieves 85-dB dynamic range at 5-MHz signal bandwidth, with an oversampling ratio of 12. The chip was fabricated in a 0.5-"m CMOS technology and operates from a single 2.5-V supply. Index Terms — Current calibration, digital-to-analog conversion, mixed analog–digital integrated circuits, multibit modulators, pipelined adders, sigma–delta modulation. I.

the low-voltage transmitter and receiver interfaces between the modem digital signal-processing engine and the high-voltage hybrid circuitry for either the central office or the remote terminal ends of the subscriber loop, configurable by metal mask option. Extensive use of digital interpolation filters in the transmitter, decimation filters in the receiver, and oversampled data converters minimize the complexity of analog filters. On-chip filtering and 14-bit data converters support echo-canceling modems without requiring external filters. With additional external filters, frequency-division duplexing is also supported. The die area is 67.5 mm P. The power dissipation in the central office and remote terminal are 600 and 760 mW, respectively. Index Terms — Asymmetric digital subscriber loop (ADSL), analog-digital conversion, analog integrated circuits, broadband communication, CMOS analog integrated circuits, Codecs, digital-analog conversion, digital filters, mixed analog-digital integrated circuits, subscriber loops. I.

Abstract—This paper presents the design and experimental results of a continuous-time 61 modulator for ADSL applications. Multibit nonreturn-to-zero (NRZ) DAC pulse shaping is used to reduce clock jitter sensitivity. The nonzero excess loop delay problem in conventional continuous-time 61 modulators is solved by our proposed architecture. A prototype third-order continuous-time 61 modulator with 5-bit internal quantization was realized in a 0.5- m double-poly triple-metal CMOS technology, with a chip area of 2.4 2.4 mm2. Experimental results show that the modulator achieves 88-dB dynamic range, 84-dB SNR, and 83-dB SNDR over a 1.1-MHz signal bandwidth with an oversampling ratio of 16, while dissipating 62 mW from a 3.3-V supply. Index Terms—Analog-to-digital conversion, CMOS analog integrated circuits, continuous-time 61 modulation, multibit internal quantization. I.

I would like to thank the following people for their contributions to this work. First and foremost, Professor Lawrence Pileggi, my dissertation advisor, has been a constant source of support throughout my time at Carnegie Mellon. This work would not have been possible without him. The dissertation committee, Professor L. Richard Carley, Professor Jeyanandh Paramesh, Professor Yang Xu, and Mr. Tony Bonaccio, provided guidance and help at various stages of this work. My fellow Ph.D. student, Gokce Keskin, was essential to this work in many ways. He was responsible for much of the digital circuit design and layout for the test chips and gathered the statistical data from the first comparator test chips. The support of IBM Research and IBM Microelectronics was crucial to the success of the project. Dr. Jean-Olivier Plouchart of IBM T. J. Watson Research Center provided a great deal of help during the laboratory testing of the flash ADC. Dr. Daniel Friedman kindly offered an internship at Watson and provided managerial support during the laboratory testing. Dr. Mehmet Soyuer, Dr. Sudhir Gowda, and Dr. Brian Floyd (now of NC State University) provided fabrication for the final two test chips and key managerial support. At IBM Microelectronics, Randy Wolf and Ida Pucino supported the fabrication of the first comparator test chip. I would also like to thank my fellow research group members, Brian Taylor, Dan Morris, Umut Arslan, and Soner Yaldiz, for many interesting discussions. The Center for Circuit and System Solutions (C2S2) provided funding for this work. IBM provided the chip fabrication and high-speed test laboratory.