We demonstrate a model, including operational semantics, for the reverse execution of stack-based code. We discuss our modification of the Kaffe implementation of the Java Virtual Machine, supporting a debugger capable of running Java bytecode backwards. We achieve reverse execution by logging the state lost during each operation or by directly reversing instructions. Our debugger has facilities for stepping, stepping over methods and running to breakpoints, in both directions. Multi-threading is supported. It is also possible to step through the bytecode when the Java source code is not available. The debugger has both a command line user interface and a graphical user interface with facilities for editing code and running the Java compiler.

The Java language specification states that every access to an array needs to be within the bounds of that array; i.e. between 0 and length - 1. Different techniques for different programming languages have been proposed to eliminate explicit bounds checks. Some of these techniques are implemented in off-the-self Java Virtual Machines (JVMs). The underlying principle of these techniques is that bounds checks can be removed when a JVM/compiler has enough information to guarantee that a sequence of accesses (e.g. inside a for-loop) is safe (within the bounds).

Dynamic correctness checking tools (a.k.a. lifeguards) can detect a wide array of correctness issues, such as memory, security, and concurrency misbehavior, in unmodified executables at run time. However, lifeguards that are implemented using dynamic binary instrumentation (DBI) often slow down the monitored application by 10–50X, while proposals that replace DBI with hardware still see 3–8X slowdowns. The remaining overhead is the cost of performing the lifeguard analysis itself. In this paper, we explore compiler optimization techniques to reduce this overhead. The lifeguard software is typically structured as a set of eventdriven handlers, where the events are individual instructions in the monitored application’s dynamic instruction stream. We propose to decouple the lifeguard checking code from the application that it is monitoring so that the lifeguard analysis can be invoked at the granularity of hot paths in the monitored application. In this way, we are able to find many more opportunities for eliminating redundant work in the lifeguard analysis, even starting with welloptimized applications and hand-tuned lifeguard handlers. Experimental results with two lifeguard frameworks—one DBI-based and one hardware-assisted—show significant reduction in monitoring overhead.

final copy of this thesis has been examined by the signatories, and we find that both the content and the form meet acceptable presentation standards of scholarly work in the above mentioned discipline. Ryan, Nathan D. (Ph.D., Computer Science)

A wide variety of application programs have inherent loop-level parallelism that can be exploited on shared-memory multiprocessor systems for performance improvement. Parallelizing compilers are available that can automatically identify and extract some of the loop-level parallelism in sequential programs. Traditional parallelizing compilers, however, often cannot extract much of the available parallelism due to the inherent limitations of compile-time information. Loops with potential data dependences that are caused by run-time values, or loops with sequential constructs (e.g. do-while loops), in particular are impossible to parallelize using these compilers. The parallelism in such loops can be exploited only by using run-time parallelization techniques since the information required to parallelize these loops is available only at run-time. Once a program has been parallelized, it is necessary to efficiently execute it in parallel to improve its performance. Compiler parallelized code cannot predetermine the number of processors a parallel code region can most efficiently use, however, especially, if the program behavior changes dynamically or the system load in a multiprogrammed environment changes as the program executes. With a static mapping assigned by the compiler, the parallel execution performance may suffer due to an insufficient workload in each parallel task, or due to resource contention when too many processes are running in the system. This thesis proposes a dynamically adaptive parallelization model based on speculative multithreading for multiprogrammed shared-memory multiprocessor systems to address the problems associated with traditional parallelizing compilers. This work first addresses the problem of extracting loop-level parallelism from progra...

This paper describes hardware methods, a lightweight and platform-independent scheme for linking real-time Java code to co-processors implemented using a hardware description language (HDL). Intended for use in embedded systems, hardware methods have similar semantics to the native methods used to interface Java code to legacy C/C++ software, but are also time-predictable, facilitating accurate worstcase execution time (WCET) analysis. By reference to several examples, the paper demonstrates the applicability of hardware methods and shows that they can (1) reduce the WCET of embedded real-time Java, and (2) improve the quality of WCET estimates in the presence of infeasible paths. 1.

Virtual machines (VMs) such as the Java VM are a popular format for running architectureneutral code in a managed runtime. Such VMs are typically implemented using a combination of interpretation and just-in-time compilation (JIT). A significant challenge for the portability of VM code is the growing popularity of multi-core architectures with specialized processing cores aimed at computation-intensive applications such as media processing. Such cores differ greatly in architectural design compared to traditional desktop processors. One such processing core is the Cell Broadband Engine’s (Cell BE) Synergistic Processing Element (SPE). An SPE is a light weight VLIW processor core with a SIMD vector instruction set. In this paper we investigate some popular interpreter optimizations and introduce new optimizations exploiting the special hardware properties offered by the Cell BE’s SPE. 1

Most of the research done to improve the performance of Java Virtual Machines (JVM’s) has focused on software implementations of the JVM specification. Very little consideration has been given to how Java programs interact with hardware resources and how hardware components can be used to improve Java performance. We generated and analyzed opcode and memory access traces for eight different Java benchmarks, finding that each Java opcode typically causes multiple memory accesses. We next investigated the effectiveness of unified and split caches at caching Java programs, using the performance of traditional compiled programs for a basis of comparison. Motivated by the subdivision of memory by the JVM specification into heap memory, constant pool data, and operand stacks, we examined the possible benefits of adding small specialized caches to hold constant pool data and stack data. We found that constant pool accesses have very low locality of reference and that the addition of a constant cache is detrimental to cache performance for large main caches. The 24 % of memory accesses made to operand stacks were found to be efficiently cached in a 64 byte cache. We simulated

this paper. The first is that of not allowing any static method inlining. Since every class in Java has certain security permissions, inlining statically could potentially violate run-time determined permissions. The second is the rule that all classes are to be linked and loaded on demand at run-time. This minimizes the initialization latency of Java programs whose class files may be on another node on the network

Abstract: Providing multi-interface device users the ability to roam between different access networks is becoming a key requirement for service providers. The availability of multiple mobile broadband access technologies together with increasing use of real time multimedia applications is creating strong demand for handover solutions that can seamlessly and securely transfer user sessions across different access technologies. In this paper, we discuss how the Copyright © 2010 Inderscience Enterprises Ltd. Integration of IEEE 802.21 services and pre-authentication framework 173 IEEE 802.21 standard and its services address the challenges of seamless mobility for multi-interface devices. We focus on a proof-of-concept implementation that integrates IEEE 802.21 services and a pre-authentication framework, to optimise handover performance in two different scenarios. The first scenario is initiated by the mobile node and the second one is initiated by the network. We present the measurement results for realising these scenarios. Finally, we describe the implementation challenges and lessons learned through