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Symbolic Boolean manipulation with ordered binarydecision diagrams
 ACM Computing Surveys
, 1992
"... Ordered BinaryDecision Diagrams (OBDDS) represent Boolean functions as directed acyclic graphs. They form a canonical representation, making testing of functional properties such as satmfiability and equivalence straightforward. A number of operations on Boolean functions can be implemented as grap ..."
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Cited by 874 (11 self)
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Ordered BinaryDecision Diagrams (OBDDS) represent Boolean functions as directed acyclic graphs. They form a canonical representation, making testing of functional properties such as satmfiability and equivalence straightforward. A number of operations on Boolean functions can be implemented as graph algorithms on OBDD
Constraint satisfaction using constraint logic programming
 Artificial Intelligence
, 1992
"... Constraint logic programming (CLP) is a new class of declarative programming languages whose primitive operations are based on constraints (e.g. constraint solving and constraint entailment). CLP languages naturally combine constraint propagation with nondeterministic choices. As a consequence, the ..."
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Cited by 73 (3 self)
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Constraint logic programming (CLP) is a new class of declarative programming languages whose primitive operations are based on constraints (e.g. constraint solving and constraint entailment). CLP languages naturally combine constraint propagation with nondeterministic choices. As a consequence, they are particularly appropriate for solving a variety of combinatorial search problems, using the global search paradigm, with short development time and efficiency comparable to procedural tools based on the same approach. In this paper, we describe how the CLP language cc(FD), a successor of CHIP using consistency techniques over finite domains, can be used to solve two practical applications: testpattern generation and car sequencing. For both applications, we present the cc(FD) program, describe how constraint solving is performed, report experimental results, and compare the approach with existing tools.
Probabilistic transfer matrices in symbolic reliability analysis of logic circuits
 ACM Transactions on Design Automation of Electronic Systems
"... We propose the probabilistic transfer matrix (PTM) framework to capture nondeterministic behavior in logic circuits. PTMs provide a concise description of both normal and faulty behavior, and are wellsuited to reliability and error susceptibility calculations. A few simple composition rules based o ..."
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Cited by 5 (2 self)
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We propose the probabilistic transfer matrix (PTM) framework to capture nondeterministic behavior in logic circuits. PTMs provide a concise description of both normal and faulty behavior, and are wellsuited to reliability and error susceptibility calculations. A few simple composition rules based on connectivity can be used to recursively build larger PTMs (representing entire logic circuits) from smaller gate PTMs. PTMs for gates in series are combined using matrix multiplication, and PTMs for gates in parallel are combined using the tensor product operation. PTMs can accurately calculate joint output probabilities in the presence of reconvergent fanout and inseparable joint input distributions. To improve computational efficiency, we encode PTMs as algebraic decision diagrams (ADDs). We also develop equivalent ADD algorithms for newly defined matrix operations such as eliminate variables and eliminate redundant variables, which aid in the numerical computation of circuit PTMs. We use PTMs to evaluate circuit reliability and derive polynomial approximations for circuit error probabilities in terms of gate error probabilities. PTMs can also analyze the effects of logic and electrical masking on error mitigation. We show that ignoring logic masking can overestimate errors by an order of magnitude. We incorporate electrical masking by computing error attenuation probabilities, based on analytical models, into an extended PTM
Selective Hardening in Early Design Steps
 13TH EUROPEAN TEST SYMPOSIUM
"... Hardening a circuit against soft errors should be performed in early design steps before the circuit is laid out. A viable approach to achieve soft error rate (SER) reduction at a reasonable cost is to harden only parts of a circuit. When selecting which locations in the circuit to harden, priority ..."
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Cited by 2 (1 self)
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Hardening a circuit against soft errors should be performed in early design steps before the circuit is laid out. A viable approach to achieve soft error rate (SER) reduction at a reasonable cost is to harden only parts of a circuit. When selecting which locations in the circuit to harden, priority should be given to critical spots for which an error is likely to cause a system malfunction. The criticality of the spots depends on parameters not all available in early design steps. We employ a selection strategy which takes only gatelevel information into account and does not use any lowlevel electrical or timing information. We validate the quality of the solution using an accurate SER estimator based on the new UGC particle strike model. Although only partial information is utilized for hardening, the exact validation shows that the susceptibility of a circuit to soft errors is reduced significantly. The results of the hardening strategy presented are also superior to known purely topological strategies in terms of both hardware overhead and protection.
HISCOAP: A Hierarchical Testability Analysis Tool
"... We describe a time and space efficient technique for evaluating the SCOAP testability measure of a circuit from its hierarchical description. Under the stuck at fault model, the SCOAP measure introduced by Goldstein is known to offer a good estimate of the controllability and observability of a give ..."
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Cited by 1 (0 self)
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We describe a time and space efficient technique for evaluating the SCOAP testability measure of a circuit from its hierarchical description. Under the stuck at fault model, the SCOAP measure introduced by Goldstein is known to offer a good estimate of the controllability and observability of a given circuit. SCOAP works on a gatelevel netlist, and can be expensive in terms of memory and computational resources when large circuits of VLSI complexity are involved. We show that this problem can be alleviated by taking advantage of a hierarchical representation of the circuit. We introduce the notion of SCOAP Expression diagrams for functional modules, which can be precomputed and stored as part of the module database. The hierarchical testability analysis program, HISCOAP reads the SCOAP Expression Diagrams for the modules used in the circuit, and evaluates the SCOAP measures in a systematic manner. Tlie program has been implemented on a Sun/SPARC workstation, and we present results on several benchmark circuits, both combinational and sequential. 1
ATestability Measure for Hierarchical Design Environments
"... In this paper a new approach is proposed tocompute testability of a combinational circuit in a hierarchical design environment. The testability of a circuit is rst computed at the functional level using the Walsh expression of the functional block, and its complexity is linear with respect to the nu ..."
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In this paper a new approach is proposed tocompute testability of a combinational circuit in a hierarchical design environment. The testability of a circuit is rst computed at the functional level using the Walsh expression of the functional block, and its complexity is linear with respect to the number of functional blocks. The functional level testability measure is then used to compute the testability at the gate/switch level. Our extensive simulation results show that the testability measure of the proposed method re ects closely to the actual testability measure (both at the functional level and the gate level) when the granularity of a functional block is much higher than that of primitive gates. 1