Evolvable hardware (EHW) has attracted increasing attention since early 1990's with the advent of easily reconfigurable hardware such as field programmable gate arrays (FPGAs). It promises to provide an entirely new approach to complex electronic circuit design and new adaptive hardware. EHW has been demonstrated to be able to perform a wide range of tasks from pattern recognition to adaptive control. However, there are still many fundamental issues in EHW which remain open. This paper reviews the current status of EHW, discusses the promises and possible advantages of EHW, and indicates the challenges we must meet in order to develop practical and large-scale EHW. 1 Introduction Evolvable hardware (EHW) refers to hardware that can change its architecture and behaviour dynamically and autonomously by interacting with its environment. At present, almost all EHW uses an evolutionary algorithm (EA) as their main adaptive mechanism. One of the key motivations behind EHW is to learn from N...

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We present in this work the application of a set of different evolutionary methodologies in the problem of electronic filter design. The main objectives are to find out which constraints in the filter topologies, if any, must be observed along the evolutionary process and to study the problem of convergence to parsimonious circuits. The new area of Evolutionary Electronics is introduced, an evolutionary methodology based on variable length representation is presented and the results on the evolution of lowpass and band-pass filters are described. 1. Introduction This work focuses on the application of evolutionary systems in engineering design. Particularly, the application of evolutionary techniques in the area of electronic design and optimisation gave birth to a new and promising area of research, Evolutionary Electronics[12][5]. The aim of this area is the creation of new automation design techniques for electronic circuits, based on the Darwinian concepts of natural selection, r...

This paper presents the HGA, a genetic algorithm written in VHDL and intended for a hardware implementation. Due to pipelining, parallelization, and no function call overhead, a hardware GA yields a significant speedup over a software GA, which is especially useful when the GA is used for real-time applications, e.g. disk scheduling and image registration. Since a general-purpose GA requires that the fitness function be easily changed, the hardware implementation must exploit the reprogrammability of certain types of field-programmable gate arrays (FPGAs), which are programmed via a bit pattern stored in a static RAM and are thus easily reconfigured. After presenting some background on VHDL, this paper takes the reader through the HGA's code. We then describe some applications of the HGA that are feasible given the state-of-the-art in FPGA technology and summarize some possible extensions of the design. Finally, we review some other work in hardware-based GAs. Contents 1 Introductio...

We have designed a highly parallel design for a simple genetic algorithm using a pipeline of systolic arrays. The systolic design provides high throughput and unidirectional pipelining by exploiting the implicit parallelism in the genetic operators. The design is significant because, unlike other hardware genetic algorithms, it is independent of both the fitness function and the particular chromosome length used in a problem. We have designed and simulated a version of the mutation array using Xilinix FPGA tools to investigate the feasibility of hardware implementation. A simple 5-chromosome mutation array occupies 195 CLBs and is capable of performing more than one million mutations per second. I. Introduction Genetic algorithms (GAs) are established search and optimization techniques which have been applied to a range of engineering and applied problems with considerable success [1]. They operate by maintaining a population of trial solutions encoded, using a suitable encoding schem...

The use of GAs in evolvable hardware is reviewed. A case is made for implementing as much of the GA in hardware as possible. The technical difficulties of using a standard GA with an FPGA are described. A new type of GA called a Ringed GA, which features only local interactions among individuals, is introduced. A new type of reconfigurable platform called the PIG is described. The use of the PIG to support local, parallel GA operations is explained. Experiments in evolving digital circuits using a ringed GA on the PIG are described. Conclusions and plans for future work are presented.