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Adaptive CMOS: From Biological Inspiration to SystemsonaChip
 PROCEEDINGS OF THE IEEE
, 2002
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A costeffective approach to the design and layout of a 14b currentsteering DAC macrocell
 IEEE TCASI
, 2004
"... Abstract—This brief discusses the economical design of a 14b currentsteering digitaltoanalog converter (DAC) macrocell for integration with other analog and digital macrocells in a systemonchip (SOC). The DAC design is targeted for a standard 0.13 m sixmetal singlepoly CMOS process. A novel ..."
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Abstract—This brief discusses the economical design of a 14b currentsteering digitaltoanalog converter (DAC) macrocell for integration with other analog and digital macrocells in a systemonchip (SOC). The DAC design is targeted for a standard 0.13 m sixmetal singlepoly CMOS process. A novel algorithm sets the switching order of individual current sources and minimizes systematic mismatch errors. The design approach minimizes total fabrication cost of the SOC without a loss to specified DAC design requirements. Total macrocell design area is 2.9 mm. Index Terms—CMOS macrocell, digitaltoanalog converter (DAC), good die yield, INL yield, SOC integration, switching algorithm, systematic error reduction. I.
CostOriented Design of a 14bit Current Steering DAC Macrocell
"... This paper presents the design concept and implementation of a 14bit current steering DAC macrocell for a SOC in 0.13um CMOS. The design approach minimizes total fabrication cost of the SOC. The paper demonstrates that using this approach smaller and economically efficient DACs will result without ..."
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This paper presents the design concept and implementation of a 14bit current steering DAC macrocell for a SOC in 0.13um CMOS. The design approach minimizes total fabrication cost of the SOC. The paper demonstrates that using this approach smaller and economically efficient DACs will result without a loss to specified design requirements. 1.
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"... This letter proposes a lowpower currentsteering digitaltoanalog converter (DAC). The proposed DAC reduces the clock power by cutting the clock signal to the currentsource cells in which the data will not be changed. The 10bit DAC is implemented using a 0.13μm CMOS process with VDD=1.2 V. Its ..."
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This letter proposes a lowpower currentsteering digitaltoanalog converter (DAC). The proposed DAC reduces the clock power by cutting the clock signal to the currentsource cells in which the data will not be changed. The 10bit DAC is implemented using a 0.13μm CMOS process with VDD=1.2 V. Its area is 0.21 mm2. It consumes 4.46 mW at a 1MHz signal frequency and 200MHz sampling rate. The clock power is reduced to 30.9 % and 36.2 % of a conventional DAC at 1.25MHz and 10MHz signal frequencies, respectively. The measured spurious free dynamic ranges are 72.8 dB and 56.1 dB at 1MHz and 50MHz signal frequencies, respectively.
A 12bit 300 MHz CMOS DAC for Highspeed System Applications
"... for highspeed system applications. The proposed DAC consists of a unit currentcell matrix for 8 MSBs and a binaryweighted array for 4 LSBs. In order to ensure the linearity of DAC, a double Centro symmetric current matrix is designed by using the Q2 random walk strategy. To minimize the feedthrou ..."
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for highspeed system applications. The proposed DAC consists of a unit currentcell matrix for 8 MSBs and a binaryweighted array for 4 LSBs. In order to ensure the linearity of DAC, a double Centro symmetric current matrix is designed by using the Q2 random walk strategy. To minimize the feedthrough and improve the dynamic performance, the drain of the switching transistors is isolated from the output lines by adding two cascoded transistors. I.
protecting it.Design Considerations for High Resolution Pipeline ADCs in Digital CMOS Technology
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Using reciprocity theorem to analyze R2R network DACs
"... Abstract. Reciprocity theorem is proposed to design and analyze R2R based DAC, which can make the complicated design and analysis of R2R based DACs simple. The detail of how to use reciprocity theorem in the design and analysis of R2R based DAC is given. The 14bit DAC designed by Reciprocity The ..."
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Abstract. Reciprocity theorem is proposed to design and analyze R2R based DAC, which can make the complicated design and analysis of R2R based DACs simple. The detail of how to use reciprocity theorem in the design and analysis of R2R based DAC is given. The 14bit DAC designed by Reciprocity Theorem has performances of 69dB SNR, 11.1 bits ENOB and 77.9dB SFDR.