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Closing the Gap Between ASIC and Custom: An ASIC Perspective
 DAC 2000
, 2000
"... We investigate the differences in speed between applicationspecific integrated circuits and custom integrated circuits when each are implemented in the same process technology, with some examples in 0.25 micron CMOS. We first attempt to account for the elements that make the performance different ..."
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Cited by 30 (0 self)
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We investigate the differences in speed between applicationspecific integrated circuits and custom integrated circuits when each are implemented in the same process technology, with some examples in 0.25 micron CMOS. We first attempt to account for the elements that make the performance different and then examine ways in which tools and methodologies may close the performance gap between applicationspecific integrated circuits and custom circuits.
DualMonotonic Domino Gate Mapping and Optimal Output Phase Assignment of Domino Logic
, 2000
"... In this paper, two problems on domino logic synthesis are addressed. A mapping method that maps the complementary logic cones independently when AND/OR logic is to be implemented, and together using dualmonotonic gates in the case of XOR/XNOR logic, is proposed. The results show up to 28.9% improv ..."
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Cited by 6 (1 self)
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In this paper, two problems on domino logic synthesis are addressed. A mapping method that maps the complementary logic cones independently when AND/OR logic is to be implemented, and together using dualmonotonic gates in the case of XOR/XNOR logic, is proposed. The results show up to 28.9% improvement in area and always show the same or better performance in delay over existing approaches. Then, a 01 integer programming formulation is provided for the output phase assignment problem for domino logic. It considers the cost difference between two polarities and enables a standard linear programming package to be used to solve the problem. The results show up to 41.0% improvement in area.
Timingdriven Partitioning and Timing Optimization of Mixed StaticDomino Implementations
, 2000
"... Domino logic is a circuit family that is wellsuited to implementing highspeed circuits. Synthesis of domino circuits is more complex than static logic synthesis due to the noninverting nature of the logic and the complex timing relationships associated with the clockscheme. In this paper, we addre ..."
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Cited by 3 (1 self)
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Domino logic is a circuit family that is wellsuited to implementing highspeed circuits. Synthesis of domino circuits is more complex than static logic synthesis due to the noninverting nature of the logic and the complex timing relationships associated with the clockscheme. In this paper, we address several problems along a domino synthesis ow. We mainly consider the problem of partitioning a circuit into static and domino regions under timing constraints. The algorithm is extended to develop a method for partitioning domino logic into two phases, with inverters permitted between the two phases, and then to a ow for general twophase staticdomino partitioning. We also address a timing veri cation and sizing optimization tool for circuits containing mixed domino and static logic.
Technology Mapping Algorithms for Domino Logic
, 2002
"... In this paper, we present an efficient algorithm for technology mapping of domino logic to a parameterized library. The algorithm is optimal for mapping trees consisting of 2input AND/OR nodes, and has a computation time that is polynomial in terms of constraint size. The mapping method is then ext ..."
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Cited by 3 (1 self)
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In this paper, we present an efficient algorithm for technology mapping of domino logic to a parameterized library. The algorithm is optimal for mapping trees consisting of 2input AND/OR nodes, and has a computation time that is polynomial in terms of constraint size. The mapping method is then extended to DAG covering that permits the implicit duplication of logic nodes. Our synthesis procedure maps the complementary logic cones independently when AND/OR logic is to be implemented, and together using dualmonotonic gates in the case of XOR/XNOR logic. The mapping procedure solves the output phase assignment problem as a preprocessing step. Based on a key observation that the output phase assignment could reduce the implementation cost due to the possible large cost di#erence between two polarities, a 01 integer linear programming formulation was formed to minimize the implementation cost. Our experimental results show the effectiveness of the proposed techniques
Timingdriven Partitioning for TwoPhase Domino and Mixed Static/Domino Implementations
 STATIC/DOMINO IMPLEMENTATIONS,” INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN
, 1999
"... Domino logic is a highperformance circuit configuration that is usually embedded in static logic environment and tightly coupled with the clocking scheme. In this paper, the timingdriven partitioning algorithms that partition a logic network between (1) static and domino implementations, and (2) t ..."
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Domino logic is a highperformance circuit configuration that is usually embedded in static logic environment and tightly coupled with the clocking scheme. In this paper, the timingdriven partitioning algorithms that partition a logic network between (1) static and domino implementations, and (2) the phases of a twophase clock, are provided. In addition, an efficient static mapping algorithm is described.
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"... Limited switch dynamic logic circuits for highspeed lowpower circuit design This paper describes a new circuit family—limited switch dynamic logic (LSDL). LSDL is a hybrid between a dynamic circuit and a static latch that combines the desirable properties of both circuit families. The paper also d ..."
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Limited switch dynamic logic circuits for highspeed lowpower circuit design This paper describes a new circuit family—limited switch dynamic logic (LSDL). LSDL is a hybrid between a dynamic circuit and a static latch that combines the desirable properties of both circuit families. The paper also describes many enhancements and extensions to LSDL that increase its logical capability. Finally, it presents the results of two multiplier designs, one fabricated in 130nm technology and one in 90nm technology. The 130 and 90nm designs respectively reach speeds up to 2.2 GHz and 8 GHz.
Paper Category Design and Synthesis
"... Domino logic has proved to be a powerful alternative to conventional CMOS in highperformance IC design. Domino logic has many advantages, including fewer transistors, faster switching speeds, and no shortcircuit or “glitching ” power consumption. This paper addresses the synthesis for mixed domino ..."
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Domino logic has proved to be a powerful alternative to conventional CMOS in highperformance IC design. Domino logic has many advantages, including fewer transistors, faster switching speeds, and no shortcircuit or “glitching ” power consumption. This paper addresses the synthesis for mixed domino/static logic to avoid large logic duplication due to the monotonic property of domino logic. We use an accurate timing and power estimation, which accounts for glitching and shortcircuit power consumption. Our method gives the designer more flexibility to optimize the circuits with a mix of domino and static logic, and make the tradeoff among several design constraints, including area, delay, and power consumption. Experimental results show the advantages of the mixed domino/static logic. On average for circuits mapped for area optimization, power is reduced by 26 % and delay is reduced by 23% without paying a large area overhead. For circuits original mapped for speed, area and delay, on average, remain the same, but power dissipation improves by 35%. 1
Delay Minimization and Technology Mapping of TwoLevel Structures and Implementation Using ClockDelayed Domino Logic
, 2000
"... This paper presents a new delay minimization and technology mapping algorithm for twolevel structures (TLS) implemented using clockdelayed (CD) domino logic. We take advantage of CD domino's highspeed, large fanin NOR and OR gates to increase the speed of a circuit by partial collapsing. Th ..."
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This paper presents a new delay minimization and technology mapping algorithm for twolevel structures (TLS) implemented using clockdelayed (CD) domino logic. We take advantage of CD domino's highspeed, large fanin NOR and OR gates to increase the speed of a circuit by partial collapsing. The algorithm is delaydriven and the delays are obtained from a characterized CD domino library. The results on eight combinational MCNC benchmark circuits show an average speed improvement of 89% for CD domino with TLS, compared to static CMOS implementations generated by Synopsys. CD domino with TLS using our tools produced on average 44% faster circuits than CD domino benchmarks minimized and mapped using Synopsys. At last, the delay results for CD domino with TLS were on average 22% better than for standard domino.
Monotonic Static CMOS and Dual V T Technology
"... We developed a methodology and tools for synthesizing monotonic static CMOS networks, which consist of alternating lowskewed and highskewed static gates. When used with a dual V T process, monotonic static CMOS can simultaneously reduce standby static power and increase performance by using low V ..."
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We developed a methodology and tools for synthesizing monotonic static CMOS networks, which consist of alternating lowskewed and highskewed static gates. When used with a dual V T process, monotonic static CMOS can simultaneously reduce standby static power and increase performance by using low V T devices in the evaluation networks and making all other devices high V T. Experimental results show monotonic static CMOS to be 1.67 times faster than traditional static CMOS. 1.