We investigate the differences in speed between applicationspecific integrated circuits and custom integrated circuits when each are implemented in the same process technology, with some examples in 0.25 micron CMOS. We first attempt to account for the elements that make the performance different and then examine ways in which tools and methodologies may close the performance gap between application-specific integrated circuits and custom circuits.

this paper is on the electronic sub-system and specifically the power dissipation of integrated circuits. This paper will first briefly motivate the topical concerns about power consumption and dissipation in integrated circuits and will then outline the automated techniques that are currently being developed to reduce power consumption.

This paper presents an algorithm to select a good set of gate sizes for the primitive gates of a standard cell library. A measurement error on a gate is dened to quantify the discrepancy resulting from replacing the size required by a synthesis sizing algorithm with a size available in a discrete cell library. The criterion for gate size selection is a set of gate sizes that minimizes the cumulative error of a prescribed measurement. Optimal solutions to the gate size selection problem targetting size and delay measurements are presented for cases when the probability distribution and the delay equations are simple. A realistic probability distribution is obtained using a sample space of gates derived fromagroup of designs that is synthesized under the semi-custom synthesis methodology [1]. A \delay-match " (minimizing delay error) and a \sizematch" (minimizing size error) set of gate sizes are obtained numerically, and are subsequently realized as discrete cell libraries. The previous group of designs are synthesized using the two selected cell libraries and two other cell libraries, one with \equal-spacing " of cell sizes and the other with \exponential-spacing " of cell sizes. The \size-match " library gives the best overall slack and area results. 1

We describe a new constructive multilevel logic synthesis system that integrates the traditionally separate technology-independent and technology-dependent stages of modern synthesis tools. Dubbed M32, this system is capable of generating circuits incrementally based on both functional as well as structural considerations. This is achieved by maintaining a dynamic structural representation of the evolving implementation and by refining it through progressive introduction of gates from a target technology library. Circuit construction proceeds from the primary inputs towards the primary outputs. Preliminary experimental results show that circuits generated using this approach are generally superior to those produced by multi-stage synthesis. I.

A new methodology for the design of low-power standard cell libraries is presented. The proposed approach addresses power consumption at various steps in the design flow, applying new design automation algorithms and incorporating innovative cell designs. CAD techniques are used to speed development of the library, allowing for quick analysis of power and delay characteristics, with subsequent feedback for redesign. The effectiveness of the proposed flow is demonstrated on several benchmark circuits implemented in a 0.35m CMOS, 1.8 volt standard cell library designed using this methodology.

: In this paper, we describe the guidelines for implementing high level macro function library to support enhanced design reusability. The conceptual framework is tested via design of large set of macro components. Three main application areas are analysed and presented in more detail: digital signal processing, telecommunication and interface functions. Design concepts are presented shortly with practical component examples. In this design concept we have combined high level components and low level layout generators to improve the quality and predictability of library components. The tools used were Synt VHDL-simulator, Synopsys v3.3b, Compass ASIC synthesizer/ChipCompiler and Mentor QuickVHDL. 1. Introduction By the year 2010 the maximum chip sizes are expected to increase to 350-800M transistors for microprocessor designs, and 210-430M gates for ASIC designs [1]. Maintaining control of these designs requires innovative design approaches and tools that support hierarchical and in...

These papers focus on the development of low power VLSI design methodology on system level modeling and circuit level modeling for power optimization. The developed transition optimization approach further merged with circuit level power optimization using Glitch minimization technique. A resistive feed back method is developed for the elimination of glitches in the CMOS circuitry, which result in power consumption and reducing performance of VLSI design. The optimized sequence is then processed through a 8-bit register bank modeled in CMOS level for data transfer to observe the glitch effect. Tanner EDA tool is used for the designing of the CMOS circuitry with resistive feedback mechanism for power optimization.