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Closing the Gap Between ASIC and Custom: An ASIC Perspective
 DAC 2000
, 2000
"... We investigate the differences in speed between applicationspecific integrated circuits and custom integrated circuits when each are implemented in the same process technology, with some examples in 0.25 micron CMOS. We first attempt to account for the elements that make the performance different ..."
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Cited by 29 (0 self)
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We investigate the differences in speed between applicationspecific integrated circuits and custom integrated circuits when each are implemented in the same process technology, with some examples in 0.25 micron CMOS. We first attempt to account for the elements that make the performance different and then examine ways in which tools and methodologies may close the performance gap between applicationspecific integrated circuits and custom circuits.
On Designing ULMBased FPGA Logic Modules
 Proceedings of SCM/SIGDA FPGA95
, 1995
"... FPGA technologies employ replicated programmable logic blocks. These can be lookup tables or more complex macrocells. In this paper, we give a method to design macrocell logic modules, based on an extension of classical work on designing Universal Logic Modules (ULM ). Specifically, we give a ..."
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Cited by 12 (5 self)
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FPGA technologies employ replicated programmable logic blocks. These can be lookup tables or more complex macrocells. In this paper, we give a method to design macrocell logic modules, based on an extension of classical work on designing Universal Logic Modules (ULM ). Specifically, we give a technique to design a class of logic modules that specialize to a large number of functions under complementations and permutations of inputs, bridging of inputs and assignment of 0/1 to inputs. Thus, a lot of functions can be implemented using a single logic module. The significance of our work lies in our ability to generate a large set of such logic modules. A choice can be made from this set based on design criteria. We demonstrate the technique by generating a set of 471 8input functions that have a much higher coverage than the 8input cells employed by Actel's FPGAs. Our functions can specialize to up to 23 times the number of functions that Actel functions can. We also show t...
GateSize Selection for Standard Cell Libraries
 in Proceedings of the IEEE/ACM International Conference on Computer Aided Design
, 1998
"... This paper presents an algorithm to select a good set of gate sizes for the primitive gates of a standard cell library. A measurement error on a gate is dened to quantify the discrepancy resulting from replacing the size required by a synthesis sizing algorithm with a size available in a discrete ce ..."
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Cited by 10 (0 self)
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This paper presents an algorithm to select a good set of gate sizes for the primitive gates of a standard cell library. A measurement error on a gate is dened to quantify the discrepancy resulting from replacing the size required by a synthesis sizing algorithm with a size available in a discrete cell library. The criterion for gate size selection is a set of gate sizes that minimizes the cumulative error of a prescribed measurement. Optimal solutions to the gate size selection problem targetting size and delay measurements are presented for cases when the probability distribution and the delay equations are simple. A realistic probability distribution is obtained using a sample space of gates derived fromagroup of designs that is synthesized under the semicustom synthesis methodology [1]. A \delaymatch " (minimizing delay error) and a \sizematch" (minimizing size error) set of gate sizes are obtained numerically, and are subsequently realized as discrete cell libraries. The previous group of designs are synthesized using the two selected cell libraries and two other cell libraries, one with \equalspacing " of cell sizes and the other with \exponentialspacing " of cell sizes. The \sizematch " library gives the best overall slack and area results. 1
Technology Mapping for High Performance Static CMOS and Pass Transistor Logic Designs
 Pages: 577
, 2001
"... Two new techniques for mapping circuits areproposed in this paper. The first method, called the oddlevel transistor replacement (OTR) method, has a goal that is similar to that of technology mapping, but without the restriction of a fixed library size, and maps a circuit to a virtual library of com ..."
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Two new techniques for mapping circuits areproposed in this paper. The first method, called the oddlevel transistor replacement (OTR) method, has a goal that is similar to that of technology mapping, but without the restriction of a fixed library size, and maps a circuit to a virtual library of complex static CMOS gates. The second technique, the Static CMOSPTL method, uses a mix of static CMOS and pass transistor logic (PTL) to realize the circuit, and utilizes the relation between PTL and binary decision diagrams. The methods are very efficient and can handle all of the ISCAS'85 benchmark circuits in minutes. Acomparison of the results with traditional technology mapping using SIS on different libraries shows an average delay reduction above 18% for OTR, and an average delay reduction above 35% for the Static CMOSPTL method, with significant savings in the area.
Technology Mapping for Low Power in Logic Synthesis
 Integration, The VLSI Journal
, 1996
"... Traditionally, three metrics have been used to evaluate the quality of logic circuits  size, speed and testability. Consequently, synthesis techniques have strived to optimize for one or more of these metrics, resulting in a large body of research in optimal logic synthesis. As a consequence of th ..."
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Cited by 1 (0 self)
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Traditionally, three metrics have been used to evaluate the quality of logic circuits  size, speed and testability. Consequently, synthesis techniques have strived to optimize for one or more of these metrics, resulting in a large body of research in optimal logic synthesis. As a consequence of this research, we have today very powerful techniques for synthesis targeting area and testability; and to a lesser extent, circuit speed. The last couple of years have seen the addition of another dimension in the evaluation of circuit quality  its power requirements. Low power circuits are emerging as an important application domain, and synthesis for low power is demanding attention. The research presented in this paper addresses one aspect of low power synthesis. It focuses on the problem of mapping a technology independent circuit to a technology specific one, using gates from a given library, with power as the optimization metric. We believe that the difficulty in obtaining accurate mo...