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Closing the Gap Between ASIC and Custom: An ASIC Perspective
 DAC 2000
, 2000
"... We investigate the differences in speed between applicationspecific integrated circuits and custom integrated circuits when each are implemented in the same process technology, with some examples in 0.25 micron CMOS. We first attempt to account for the elements that make the performance different ..."
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We investigate the differences in speed between applicationspecific integrated circuits and custom integrated circuits when each are implemented in the same process technology, with some examples in 0.25 micron CMOS. We first attempt to account for the elements that make the performance different and then examine ways in which tools and methodologies may close the performance gap between applicationspecific integrated circuits and custom circuits.
Optimized powerdelay curve generation for standard cell ICs, 2002
 ICCAD 2002. IEEE/ACM International Conference on Computer Aided Design
, 2002
"... An effective way to compare logic techniques, logic families, or cell libraries is by means of power (or area) versus delay plots, since the efficiency of achieving a particular delay is of crucial significance. In this paper we describe a method of producing an optimized power versus delay curve ..."
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An effective way to compare logic techniques, logic families, or cell libraries is by means of power (or area) versus delay plots, since the efficiency of achieving a particular delay is of crucial significance. In this paper we describe a method of producing an optimized power versus delay curve for a combinational circuit. We then describe a method for comparing the relative merits of a set of power versus delay curves for a circuit, each generated with a different cell library. Our results indicate that very few combinational functions need to be in a cell library, at most 11. The powerdelay points achieved by Design Compiler from Synopsys using the stateoftheart Artisan SageX library compare unfavorably to our approach. In terms of minimum energydelay product, our approach is superior by 79 % on average. Our approach yields the same delay points with a 107 % savings in power consumption, on average. We also show that the specified VDD for a process technology should only be used for the absolute fastest implementations of a circuit. 1.
On Designing ULMBased FPGA Logic Modules
 Proceedings of SCM/SIGDA FPGA95
, 1995
"... FPGA technologies employ replicated programmable logic blocks. These can be lookup tables or more complex macrocells. In this paper, we give a method to design macrocell logic modules, based on an extension of classical work on designing Universal Logic Modules (ULM ). Specifically, we give a ..."
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FPGA technologies employ replicated programmable logic blocks. These can be lookup tables or more complex macrocells. In this paper, we give a method to design macrocell logic modules, based on an extension of classical work on designing Universal Logic Modules (ULM ). Specifically, we give a technique to design a class of logic modules that specialize to a large number of functions under complementations and permutations of inputs, bridging of inputs and assignment of 0/1 to inputs. Thus, a lot of functions can be implemented using a single logic module. The significance of our work lies in our ability to generate a large set of such logic modules. A choice can be made from this set based on design criteria. We demonstrate the technique by generating a set of 471 8input functions that have a much higher coverage than the 8input cells employed by Actel's FPGAs. Our functions can specialize to up to 23 times the number of functions that Actel functions can. We also show t...
GateSize Selection for Standard Cell Libraries
 in Proceedings of the IEEE/ACM International Conference on Computer Aided Design
, 1998
"... This paper presents an algorithm to select a good set of gate sizes for the primitive gates of a standard cell library. A measurement error on a gate is dened to quantify the discrepancy resulting from replacing the size required by a synthesis sizing algorithm with a size available in a discrete ce ..."
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This paper presents an algorithm to select a good set of gate sizes for the primitive gates of a standard cell library. A measurement error on a gate is dened to quantify the discrepancy resulting from replacing the size required by a synthesis sizing algorithm with a size available in a discrete cell library. The criterion for gate size selection is a set of gate sizes that minimizes the cumulative error of a prescribed measurement. Optimal solutions to the gate size selection problem targetting size and delay measurements are presented for cases when the probability distribution and the delay equations are simple. A realistic probability distribution is obtained using a sample space of gates derived fromagroup of designs that is synthesized under the semicustom synthesis methodology [1]. A \delaymatch &quot; (minimizing delay error) and a \sizematch&quot; (minimizing size error) set of gate sizes are obtained numerically, and are subsequently realized as discrete cell libraries. The previous group of designs are synthesized using the two selected cell libraries and two other cell libraries, one with \equalspacing &quot; of cell sizes and the other with \exponentialspacing &quot; of cell sizes. The \sizematch &quot; library gives the best overall slack and area results. 1
Technology Mapping for High Performance Static CMOS and Pass Transistor Logic Designs
 Pages: 577
, 2001
"... Two new techniques for mapping circuits areproposed in this paper. The first method, called the oddlevel transistor replacement (OTR) method, has a goal that is similar to that of technology mapping, but without the restriction of a fixed library size, and maps a circuit to a virtual library of com ..."
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Two new techniques for mapping circuits areproposed in this paper. The first method, called the oddlevel transistor replacement (OTR) method, has a goal that is similar to that of technology mapping, but without the restriction of a fixed library size, and maps a circuit to a virtual library of complex static CMOS gates. The second technique, the Static CMOSPTL method, uses a mix of static CMOS and pass transistor logic (PTL) to realize the circuit, and utilizes the relation between PTL and binary decision diagrams. The methods are very efficient and can handle all of the ISCAS'85 benchmark circuits in minutes. Acomparison of the results with traditional technology mapping using SIS on different libraries shows an average delay reduction above 18% for OTR, and an average delay reduction above 35% for the Static CMOSPTL method, with significant savings in the area.
Technology Mapping for Low Power in Logic Synthesis
 Integration, The VLSI Journal
, 1996
"... Traditionally, three metrics have been used to evaluate the quality of logic circuits  size, speed and testability. Consequently, synthesis techniques have strived to optimize for one or more of these metrics, resulting in a large body of research in optimal logic synthesis. As a consequence of th ..."
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Traditionally, three metrics have been used to evaluate the quality of logic circuits  size, speed and testability. Consequently, synthesis techniques have strived to optimize for one or more of these metrics, resulting in a large body of research in optimal logic synthesis. As a consequence of this research, we have today very powerful techniques for synthesis targeting area and testability; and to a lesser extent, circuit speed. The last couple of years have seen the addition of another dimension in the evaluation of circuit quality  its power requirements. Low power circuits are emerging as an important application domain, and synthesis for low power is demanding attention. The research presented in this paper addresses one aspect of low power synthesis. It focuses on the problem of mapping a technology independent circuit to a technology specific one, using gates from a given library, with power as the optimization metric. We believe that the difficulty in obtaining accurate mo...
Power and Area Optimization by Reorganizing CMOS Complex Gate Circuits
"... Thispaper proposes a method for achieving lowpower controllogic modules using a combination of CMOS complex gate reorganization, transistor size optimization, and transistor layout. Complex gate reorganization minimizes transistor count and net count without changing the functionality of the cir ..."
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Thispaper proposes a method for achieving lowpower controllogic modules using a combination of CMOS complex gate reorganization, transistor size optimization, and transistor layout. Complex gate reorganization minimizes transistor count and net count without changing the functionality of the circuit. Transistor sizing and layout are interdependent, the optimization of one results in the optimization of the other. The authors applied the reorganization method to a 2400transistor circuit, and succeeded in reducing the transistor count by 12%, and the net count by 13%. Transistor sizing and layout compaction reduced the average transistor size by one eighth, while the same delay was maintained. Power dissipation was cut to less than half, even when wiring capacitances were dominant. 1
DAG Based LibraryFree Technology Mapping
"... This paper proposes a libraryfree technology mapping algorithm to reduce delay in combinational circuits. The algorithm reduces the overall number of series transistors through the longest path, considering that each cell network has to obey to a maximum admitted chain. The number of series transis ..."
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This paper proposes a libraryfree technology mapping algorithm to reduce delay in combinational circuits. The algorithm reduces the overall number of series transistors through the longest path, considering that each cell network has to obey to a maximum admitted chain. The number of series transistors is computed in a Boolean way, reducing the structural bias. The mapping algorithm is performed on a Directed Acyclic Graph (DAG) description of the circuit. Preliminary results for delay were obtained through SPICE simulations. When compared to the SIS technology mapping, the proposed method shows significant delay reductions, considering circuits mapped with different libraries. Categories and Subject Descriptors B.6.3 [Logic Design]: Design Aids – automatic synthesis, optimization.
Yieldaware Placement Optimization
"... In this paper we describe a methodology addressing the issue of avoiding yield hazardous cell abutments during placement. This is made possible by accurate characterization of the yield penalty associated with particular celltocell interactions. Of course characterizing all possible cell abutments ..."
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In this paper we describe a methodology addressing the issue of avoiding yield hazardous cell abutments during placement. This is made possible by accurate characterization of the yield penalty associated with particular celltocell interactions. Of course characterizing all possible cell abutments in a library of 600+ cells is impractical. We will describe some simple heuristics that attempt to resolve the cell abutment precharacterization complexity. Finally we will show a possible implementation of the proposed yieldaware placement optimization methodology and demonstrate the potential of cell interaction penalty characterization for a 90nm design test case. 2
Abstract Anatomy of a Hardware Compiler
"... Programminglanguage compilers generate code targeted to machines with fixed architectures, either parallel or serial. Compiler techniques can also be used to generate the hardware on which these programming languages are executed. In this paper we demonstrate that many compilation techniques deve ..."
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Programminglanguage compilers generate code targeted to machines with fixed architectures, either parallel or serial. Compiler techniques can also be used to generate the hardware on which these programming languages are executed. In this paper we demonstrate that many compilation techniques developed for programming languages are applicable to compilation of registertransfer hardware designs. Our approach uses a typical syntaxdirected translation+ global optimization + local optimization + code generation + peephole optimization method. In this paper we will describe ways in which we have both followed and diverged from traditional compiler approaches to these problems and compare our approach to other compiler oriented approaches to hardware compilation. 1