The effectiveness of I DDQ testing in deep sub-micron is threatened by the increased transistor sub-threshold leakage current. In this article, we survey possible solutions and propose a deep sub-micron I DDQ test mode. The methodology provides means for unambiguous measurements of I DDQ components and defect diagnosis. The effectiveness of the test mode is demonstrated with a real life example. 1 Introduction Static CMOS circuits have very low quiescent current or I DDQ . Most of the manufacturing defects in CMOS ICs, exhibit state dependent elevated I DDQ . Therefore, I DDQ testing is a powerful test method for manufacturing process defects detection. The effectiveness of an I DDQ based test method is incomparable in quality improvement, test complexity and test cost reduction [1]. However, one of the critical requirements of I DDQ testing is the accurate measurement of an extremely small current at the VDD or VSS terminal of the Device Under Test (DUT). Typically, the I DDQ thres...

that I have read this dissertation and that in my opinion it is fully adequate,

Unipolar devices constructed from ferromagnetic semiconducting materials with variable magnetization direction are shown theoretically to behave very similarly to nonmagnetic bipolar devices such as the p − n diode and the bipolar (junction) transistor. Such devices may be applicable for magnetic sensing, nonvolatile memory, and reprogrammable logic. 1 Until recently the emerging field of magnetoelectronics has focused on magnetic metals for conducting components [1]. Multilayer magnetoelectronic devices, such as giant magnetoresistive (GMR) [2] and magnetic tunnel junction (MTJ) [3–5] devices, have revolutionized magnetic sensor technology and hold promise for reprogrammable logic and nonvolatile memory applications. The performance of these devices improves as the spin polarization of the constituent material approaches 100%, and thus there are continuing efforts to find 100% spin-polarized conducting materials. Doped magnetic semiconductors are a promising direction towards such materials, for the band-width of the occupied carrier states is narrow. For example, for nondegenerate carriers

...................................................................................................................................... viii List of publications .......................................................................................................................ix Chapter 1: Introduction..................................................................................................................1 1.1 Scope and overall research contribution..............................................................................1 1.2 Motivation............................................................................................................................2 1.2.1 The interconnect problem .............................................................................................2 1.2.2 Capabilities and limitations of electrical interconnects................................................4 1.2.3 Advantages of optical interconnects ......................................

An electro-optical measurement system for the DC characterization of visible detectors for CMOS compatible vision chips is presented which can help designers to characterize these detectors. The measurement system has been designed to be versatile, fast and easily expandable and used. Two different set-up's for the measurement of the spectral response and the optical dynamic range of the detectors are described in detailed. Measurements of the spectral response are done with a fully computer controlled set-up, avoiding tedious and inaccurate measurements. A description of the different detectors available in a CMOS process is also given, together with the parameters affecting their response and a set of test structures which can be useful for the characterization of the detectors. 1. Introduction In the last years there has been a growing interest in the development of CMOS compatible imagers which can substitute CCD cameras in imaging applications [1], overcoming the limitations of ...

Abstract We present thermally stimulated current (TSC) spectra measured on asymmetric p-n-junctions fabricated from detector grade silicon. A multitude of characteristic deep levels generated by fast neutron induced damage with fluences ranging from 10 12 cm -2 to 10 14 cm -2 were observed. The TSC spectra were found to depend strongly on both the filling conditions and the electric field strength in the device. The filling of the deep levels has been investigated in detail by varying the current, temperature, and duration of the free carrier injection pulse. The corresponding observations in conjunction with a delayed heating analysis allow a tentative identification of the complex defects VO i , C i O i , C i C s , and the divacancy VV. 1 1 Introduction Introduction It is now largely accepted that the radiation induced degradation, i.e. the doping changes, the leakage current increase, and the deterioration of the charge collection, decides on a successful operation of si...

ABSTRACT: This paper presents the electrothermal simulation of integrated thin film resistors. Both the thermal and electrical problem is tackled by a semi-analytical method, without the need of generating an equivalent distributed network. As the electrical conductivity is temperature dependent, self-heating of the resistor will alterate the current distribution, leading to a non-uniform power dissipation. This then provokes a change of the temperature distribution, explaining the electrothermal coupling. Examples are given for various practical resistor designs. After a few iterations stable values for the electrical and thermal resistance and temperature and power distributions are obtained. The results show that even if one would anticipate the self-heating process based on an estimated average temperature, the behaviour will still deviate from the original design. This is caused entirely by the non-uniformity of the distributions inside the component.

A senior colleague once told me that to finish a doctorate, one not only require being very hardworking, but also extremely patient. He didn’t mention about any intellectual abilities though. At the end of this long journey, I understood what he exactly meant. During my Ph.D. studies, I went through lots of academic and mental ups and downs. I want to thank everybody who supported me in any aspect during this period. First and foremost, I thank my parents, my Aai-Baba, who always seemed to be very close to me, even though they were thousands of miles away in India. I thank them for their unconditional love and faith in me. I also thank my brothers, Ajay and Vijay dada, and my sister-in-laws, Mrinal and Anjali Vahini, for supporting me throughout this period. There wasn’t a single day passed when I didn’t remember Aboli, Ashay and Aswin, the adorable kids in the family. It was extremely difficult to stay away from such a loving family, and very frustrating not to be able to meet them very often. But my friends made the stay not only easier, but a memorable one. I thank Laxmikant, Sunil, Amol, Naveen and Nagesh for a such a nice time. With them, it was like a home away from home. I would treasure all the happy

We investigate defects in CMOS domino gates and derive the test conditions for them. Very-Low-Voltage Testing can improve the defect coverage, which we define as the maximum detectable resistance, of intra-gate and inter-gate resistive shorts. We also propose a new keeper design for CMOS domino circuits. The new keeper design has low performance impact and is best useful for small CMOS domino gates. Keepers can eliminate the floating nodes in CMOS domino logic gates. 1.

Abstract-Recent efforts are being focussed on improving the breakdown voltage (BV) of InAlAdInGaAs MODFET’s on InP towards high-power applications. A detailed understanding of the physics of breakdown in these devices is still lacking. In this work, we carry out a study of off-state breakdown on state-of-the-art MODFET’s in this material system. Through a combination of a surface-depleted cap and mesa-sidewall isolation the devices have BV’s of around 10 V. We find that BV shows a negative temperature coefficient and also decreases with a higher InAs mole fraction in the channel. As we have recently found in InAIAdn+-InGaAs HFET’s, off-state breakdown appears to be a two-step process. First, electrons are emitted by thermionic-field emission from the gate to the insulator. Second, as a consequence of the large electric field in the insulator and the substantial AEc between insulator and channel, they enter the channel hot, into the high-field drain-gate region, and relax their energy through impact-ionization. This combined hypothesis is able to explain why the MODFET breakdown voltage depends on both channel and insulator design parameters. I.