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26
Geometric Interconnection and Placement Algorithms
, 1995
"... This dissertation examines a number of geometric interconnection, partitioning, and placement problems arising in the field of VLSI physical design automation. In particular, many of the results concern the geometric Steiner tree problem: given a set of terminals in the plane, find a minimumlength ..."
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Cited by 10 (3 self)
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This dissertation examines a number of geometric interconnection, partitioning, and placement problems arising in the field of VLSI physical design automation. In particular, many of the results concern the geometric Steiner tree problem: given a set of terminals in the plane, find a minimumlength interconnection of those terminals according to some geometric distance metric. Two new algorithms are introduced that compute optimal rectilinear Steiner trees. Both are provably faster than any previous algorithm for instances small enough to solve in practice, and both are also fast in practice. The first algorithm is a dynamic programming algorithm based on decomposing a rectilinear Steiner tree into full trees. A full tree is a Steiner tree in which every terminal is a leaf. Its time complexity is O(n3^n), where n is the number of terminals. The second algorithm modifies the first by the use of fullset screening, which is a process by which some candidate full trees are eliminated f...
MINCE: A static global variableordering heuristic for sat search and bdd manipulation
 Journal of Universal Computer Science (JUCS
, 2004
"... Abstract: The increasing popularity of SAT and BDD techniques in formal hardware verification and automated synthesis of logic circuits encourages the search for additional speedups. Since typical SAT and BDD algorithms are exponential in the worstcase, the structure of realworld instances is a nat ..."
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Cited by 9 (1 self)
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Abstract: The increasing popularity of SAT and BDD techniques in formal hardware verification and automated synthesis of logic circuits encourages the search for additional speedups. Since typical SAT and BDD algorithms are exponential in the worstcase, the structure of realworld instances is a natural source of improvements. While SAT and BDD techniques are often presented as mutually exclusive alternatives, our work points out that both can be improved via the use of the same structural properties of instances. Our proposed methods are based on efficient problem partitioning and can be easily applied as preprocessing with arbitrary SAT solvers and BDD packages without modifying the source code of SAT/BDD tools. Finding a better variable ordering is a well recognized problem for both SAT solvers and BDD packages. Currently, the best variableordering algorithms are dynamic, in the sense that they are invoked many times in the course of the host algorithm that solves SAT or manipulates BDDs. Examples include the DLCS ordering for SAT solvers and variable sifting during BDD manipulations. In this work we propose a universal variableordering algorithm MINCE (MIN Cut Etc.) that preprocesses a given Boolean formula in CNF. MINCE is completely independent from target SAT algorithms and in some cases outperforms both the variable state independent
Temperature measurement and equilibrium dynamics of simulated annealing placements
 IEEE Trans. on CAD
, 1990
"... AbstractOne way to alleviate the heavy computation required by simulated annealing placement algorithms is to replace a significant fraction of the higher or middle temperatures with a faster heuristic, and then follow it with simulated annealing. A crucial issue in this approach is the determinat ..."
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Cited by 8 (1 self)
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AbstractOne way to alleviate the heavy computation required by simulated annealing placement algorithms is to replace a significant fraction of the higher or middle temperatures with a faster heuristic, and then follow it with simulated annealing. A crucial issue in this approach is the determination of the starting temperature for the simulated annealing phasea temperature should be chosen that causes an appropriate amount of optimization to he done, but makes good use of the structure provided by the heuristic. This paper presents a method for measuring the temperature of an existing placement. The approach is based on the measurement of the probability distribution of the change in cost function, P(AC), and makes the assumption that the placement is in simulated annealing equilibrium at some temperature. The temperature of placements produced both by a simulated annealing and a mincut placement algorithm are measured, and good agreement with known temperatures is obtained. The P ( A C) distribution
Characterization of Feasible Retimings
, 2001
"... We present a theorem which characterizes all feasible retimings for a stronglyconnected graph. For such graphs, we give necessary and sufficient conditions for the achievability of a chosen target retiming. We describe an application which combines floorplanning and retiming which utilizes this cha ..."
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Cited by 7 (1 self)
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We present a theorem which characterizes all feasible retimings for a stronglyconnected graph. For such graphs, we give necessary and sufficient conditions for the achievability of a chosen target retiming. We describe an application which combines floorplanning and retiming which utilizes this characterization. Experimental results show our techniques yield superior clock frequencies with a minor increase in wirelength.
Relaxed Partitioning Balance Constraints in TopDown Placement
 in ASIC’98
"... Recent work of Simon and Teng [17] observes that the recursive bisection (i.e., bipartitioning with equal partition target areas, and minimum possible allowed deviation from targets) heuristic for k way minimumcut graph partitioning can have unbounded error, but that relaxing the balance constra ..."
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Cited by 5 (1 self)
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Recent work of Simon and Teng [17] observes that the recursive bisection (i.e., bipartitioning with equal partition target areas, and minimum possible allowed deviation from targets) heuristic for k way minimumcut graph partitioning can have unbounded error, but that relaxing the balance constraints in each call to the bipartitioning engine can result in kway net cuts within a small (O(logk)) factor of optimal. Motivated by this result, we experimentally determine whether relaxing the traditional exact bisection constraint in a topdown partitioningbased placement tool can improve the resulting cutsizes, and hence total wirelength, of the placement solution. We find that this simple change reduces total wirelength by up to several percent, with no change in placement uniformity and under 10% runtime penalty. Finally, we observe that the stability (predictability) of the placement process appears unimpaired by this modification: both wirelength stability, and stability of Rent par...
Largescale circuit placement: Gap and promise
 in ICCAD ’03: Proceedings of the 2003 IEEE/ACM international conference on Computeraided design
"... Placement is one of the most important steps in the RTLtoGDSII synthesis process, as it directly defines the interconnects, which have become the bottleneck in circuit and system performance in deep submicron technologies. The placement problem has been studied extensively in the past 30 years. How ..."
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Cited by 5 (1 self)
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Placement is one of the most important steps in the RTLtoGDSII synthesis process, as it directly defines the interconnects, which have become the bottleneck in circuit and system performance in deep submicron technologies. The placement problem has been studied extensively in the past 30 years. However, recent studies show that existing placement solutions are surprisingly far from optimal. The first part of this tutorial summarizes results from recent optimality and scalability studies of existing placement tools. These studies show that the results of leading placement tools from both industry and academia may be up to 50 % to 150 % away from optimal in total wirelength. If such a gap can be closed, the corresponding performance improvement will be equivalent to several technologygeneration advancements. The second part of the tutorial highlights the recent progress on largescale circuit placement, including techniques for wirelength minimization, routability optimization, and performance optimization.
New theoretical results on quadratic placement
 in Integration – a VLSI Journal Jens Vygen ICCAD 2002 Placement Tutorial 120
"... Current tools for VLSI placement are based either on quadratic placement, or on mincut heuristics, or on simulated annealing. For the most complex chips with millions of movable objects, algorithms based on quadratic placement seem to yield the best results within reasonable time. In this paper we ..."
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Cited by 2 (1 self)
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Current tools for VLSI placement are based either on quadratic placement, or on mincut heuristics, or on simulated annealing. For the most complex chips with millions of movable objects, algorithms based on quadratic placement seem to yield the best results within reasonable time. In this paper we prove several new theoretical results on quadratic placement. We point out connections to random walks and electrical networks. Moreover, we argue that quadratic placement has, in contrast to the other approaches, some welldefined stability properties. Finally, we consider the question how to choose the weights of the clique edges representing a multiterminal net optimally.
PARALLEL ALGORITHMS FOR PLACEMENT AND ROUTING IN VLSI DESIGN
, 1991
"... The computational requirements for high quality synthesis, analysis, and verification of VLSI designs have rapidly increased with the fast growing complexity of these designs. Research in the past has focused on the development of heuristic algorithms, special purpose hardware accelerators, or paral ..."
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Cited by 2 (0 self)
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The computational requirements for high quality synthesis, analysis, and verification of VLSI designs have rapidly increased with the fast growing complexity of these designs. Research in the past has focused on the development of heuristic algorithms, special purpose hardware accelerators, or parallel algorithms for the numerous design tasks to decrease the tirn,e required for solution. In this thesis, we propose two new parallel algorithms for two VLSI synthesis tasks, standard cell placement and global routing. The first algorithm, a parallel algorithm for global routing, uses hierarchical techniques to decompose the routing problem into independent routing subproblems that are solved in parallel. Results are then presented which compare the routing quality to the results of other published global routers and which evaluate the speedups attained. The second algorithm, a parallel algorithm for cell placement and global routing, hierarchically integrates a quadrisection placement algorithrr{, a bisection placement algorithm, and the previous global routing algorithm. Unique partitioning techniques are used to decompose the various stages of the algorithm into independent tasks which can be evaluated in parallel. Finally, we present results which evaluate the various algorithm alternatives and compare the algorithm performance to other placement programs, and we present measurements on the parallel speedups available.
Optimal Folding Of Standard And Custom Cells
 ACM Transactions on Design Automation of Electronic Systems
, 1996
"... We study the problem of folding an ordered list of standard and custom cells into rows of a chip so as to minimize either the routing area or the total chip area. Nine versions of the folding problem are formulated and fast polynomail time algorithms are obtained for each. Two of our formulations ..."
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Cited by 1 (1 self)
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We study the problem of folding an ordered list of standard and custom cells into rows of a chip so as to minimize either the routing area or the total chip area. Nine versions of the folding problem are formulated and fast polynomail time algorithms are obtained for each. Two of our formulations correspond to problems formulated in [PAIK93] for the folding of a stack of bitslice components. Our algorithms for these two formulations are asymptotically superior to those of [PAIK93].
Some Issues in Design of Distributed Deductive Databases
 Science
, 1996
"... The design of a distributed deductive database system differs from the design of conventional nondistributed deductive database systems in that it requires design of distribution of both the database and rulebase. In this paper, we address the rule allocation problem. We consider minimization of da ..."
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Cited by 1 (0 self)
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The design of a distributed deductive database system differs from the design of conventional nondistributed deductive database systems in that it requires design of distribution of both the database and rulebase. In this paper, we address the rule allocation problem. We consider minimization of data communication cost during rule execution as a primary basis for rule allocation. The rule allocation problem can be stated in terms of a directed acyclic graph, where nodes represent rules or relations, and edges represent either dependencies between rules or usage of relations by rules. The arcs are given weights representing volume of data that need to flow between the connected nodes. We show that rule allocation problem is NPcomplete. Next, we propose a heuristic for nonreplicated allocation based on successively combining adjacent nodes for placement at same site which are connected by highest weight edge, and study its performance visavis the enumerative algorithm for optimal all...