This paper presents a new polynomial-time algorithm for computing lower bounds on the number of functional units (FUs) of each type required to schedule a data flow graph in a specified number of control steps. A formal approach is presented that is guaranteed to find the tightest possible bounds that can be found by relaxing either the precedence constraints or integrality constraints on the scheduling problem. This tight, yet fairly efficient, bounding method can be used to estimate FU area, to generate resource constraints for reducing the search space, or in conjunction with exact techniques for efficient optimal design space exploration. I. Introduction One of the central problems in high-level synthesis is the scheduling problem -- the problem of mapping operations onto control steps in the proper order. The process of solving the scheduling problem can be viewed as the process of exploring a 2-dimensional (2D) design space, with axes representing time (schedule length) and are...

In this paper, we present a comprehensive technique for lower bound estimation (LBE) of resources from behavioral descriptions. Previous work has focused on LBE techniques that use very simple cost models which primarily focus on the functional unit resources. Our cost model accounts for storage resources in addition to functionalresources. Our timing model uses a finer granularity that permits the modeling of functional unit, register and interconnect delays. We tested our LBE technique for both functional unit and storage requirements on several high-level synthesis benchmarks and observed near-optimal results.

This paper describes an exact solution methodology, implemented in Rensselaer's Voyager design space exploration system, for solving the scheduling problem in a 3dimensional (3D) design space: the usual 2D design space (which trades off area and schedule length), plus a third dimension representing clock length. Unlike design space exploration methodologies which rely on bounds or estimates, this methodology is guaranteed to find the globally optimal solution to the 3D scheduling problem. Furthermore, this methodology efficiently prunes the search space, eliminating provably inferior design points through: (1) a careful selection of candidate clock lengths, and (2) tight bounds on the number of functional units of each type or on the schedule length. 1 Introduction In high-level synthesis, the process of solving the scheduling problem can be viewed as the process of exploring a 2-dimensional (2D) design space, with axes representing time (schedule length) and area (ideally total area...

This paper describes an exact solution methodology, implemented in Rensselaer's Voyager design space exploration system, for solving the scheduling problem in a 3dimensional (3D) design space: the usual 2D design space (which trades off area and schedule length), plus a third dimension representing clock length. Unlike design space exploration methodologies which rely on bounds or estimates, this methodology is guaranteed to find the globally optimal solution to a 3D scheduling problem. Furthermore, this methodology efficiently prunes the search space, eliminating provably inferior design points through: (1) a careful selection of candidate clock lengths, and (2) tight bounds on the number of functional units or on the schedule length. Both chaining and multi-cycle operations are supported. I. Introduction High-level synthesis is the design task of converting a behavioral description of a digital system into a registertransfer level design that implements that behavior. One of the cen...

In this paper a unified approach of lower bound functional area and cycle budget estimations is presented to predict area--delay characteristics of designs at system level. The estimations are mainly based on relaxing precedence constraints in a behavioral design description and are the most accurate estimations reported to date. 1. Introduction In high--level synthesis, a data path consisting of modules (i.e. functional units), registers and interconnection units is synthesized from a behavioral design description [McFa90]. Such a description is represented by a data flow graph (DFG), which is a translation of an algorithmic specification in a hardware description language [Eijnd92]. The ability to predict the area--delay characteristics of designs without actually implementing them is important in producing quality designs in a reasonable time, and is therefore an important part of an (interactive) system design environment [Fleu93]. If a design will be part of a larger system, then...

We present an integrated approach aimed at predicting layout area needed to implement a behavioral description for a given performance goal. Our approach is novel because: (1) it accounts for all types of RT level components (FUs, buses, registers), (2) it is highly flexible, allowing the designer to tradeoff one type of resources with another, and considers dependencies between these different types, (3) it is vertically integrated to include provably accurate physical level estimators, and hence provides realistic accounting of layout effects, and (4) it uses a timing model with finer granularity, accounting for various delays in RTL datapaths. We demonstrate our technique on a variety of HLS benchmarks and show that efficient and effective design space exploration can be accomplished using this technique.

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This paper presents a novel approach to algebraic optimization of data-flow graphs in the domain of computationally intensive applications. The presented approach is based upon the paradigm of simulated evolution which has been proven to be a powerful method for solving large non-linear optimization problems. We introduce a genetic algorithm with a new chromosomal representation of dataflow graphs that serves as a basis for preserving the correctness of algebraic transformations and allows an efficient implementation of the genetic operators. Furthermore, we introduce a new class of hardware-related transformation rules which for the first time allow to take existing component libraries into account. The efficiency of our method is demonstrated by encouraging experimental results for several standard benchmarks. 1 Introduction The very first step in the design-flow of digital systems is concerned with formulating the behavioral specification in a hardware description language such as ...

In this paper, we present a design exploration framework, called WIZARD, which aims at finding module selections leading to acceptable designs while considering scheduling and resource binding under latency, and power constraints. The framework contains two phases: choosing the resource configuration, and determining a module binding for each resource. We introduce a powerful model, called acceptability function which models design objectives, based on tradeoffs among different design constraints as well as users' willingness of accepting a design. Module utility measure cooperating with inclusion scheduling is a key to the success of the method. The module utility reects the usefulness of the module based on the acceptability function. Inclusion scheduling is a basic tool to calculate the number of generic resources as well as determine module usefulness. A heuristic which perturbs module utility values based on the given acceptability function until they lead to superior selec...

A Unified Lower Bound Estimation Technique for High-Level Synthesis The importance of effective lower bound estimation (LBE) techniques is well-established in HighLevel Synthesis (HLS), since it allows more efficient exploration of the design space while providing other HLS tools with the capability of predicting the effect of specific tools on the design space. Much of previous work has focused on LBE techniques that use very simple cost models which primarily focus on the functional unit resources. With the push towards sub-micron technologies, simple models that use functional unit resources alone are not accurate enough to allow effective design space exploration since the effects of storage and interconnect can indeed dominate the cost function. In this paper, we present an integrated approach aimed at predicting lower bounds on hardware resources needed to implement a behavioral description within a given amount of time. Our area cost model accounts for storage (register) and int...