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49
Computing Lower Bounds on Functional Units Before Scheduling
 IEEE Transactions on Very Large Scale Integration (VLSI) Systems
, 1994
"... This paper presents a new polynomialtime algorithm for computing lower bounds on the number of functional units (FUs) of each type required to schedule a data flow graph in a specified number of control steps. A formal approach is presented that is guaranteed to find the tightest possible bounds th ..."
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Cited by 32 (6 self)
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This paper presents a new polynomialtime algorithm for computing lower bounds on the number of functional units (FUs) of each type required to schedule a data flow graph in a specified number of control steps. A formal approach is presented that is guaranteed to find the tightest possible bounds that can be found by relaxing either the precedence constraints or integrality constraints on the scheduling problem. This tight, yet fairly efficient, bounding method can be used to estimate FU area, to generate resource constraints for reducing the search space, or in conjunction with exact techniques for efficient optimal design space exploration. I. Introduction One of the central problems in highlevel synthesis is the scheduling problem  the problem of mapping operations onto control steps in the proper order. The process of solving the scheduling problem can be viewed as the process of exploring a 2dimensional (2D) design space, with axes representing time (schedule length) and are...
Comprehensive Lower Bound Estimation from Behavioral Descriptions
, 1994
"... In this paper, we present a comprehensive technique for lower bound estimation (LBE) of resources from behavioral descriptions. Previous work has focused on LBE techniques that use very simple cost models which primarily focus on the functional unit resources. Our cost model accounts for storage res ..."
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Cited by 27 (2 self)
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In this paper, we present a comprehensive technique for lower bound estimation (LBE) of resources from behavioral descriptions. Previous work has focused on LBE techniques that use very simple cost models which primarily focus on the functional unit resources. Our cost model accounts for storage resources in addition to functionalresources. Our timing model uses a finer granularity that permits the modeling of functional unit, register and interconnect delays. We tested our LBE technique for both functional unit and storage requirements on several highlevel synthesis benchmarks and observed nearoptimal results.
A Solution Methodology for Exact Design Space Exploration in a ThreeDimensional Design Space
 IEEE Trans. on VLSI Systems
, 1997
"... This paper describes an exact solution methodology, implemented in Rensselaer's Voyager design space exploration system, for solving the scheduling problem in a 3dimensional (3D) design space: the usual 2D design space (which trades off area and schedule length), plus a third dimension represen ..."
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Cited by 21 (2 self)
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This paper describes an exact solution methodology, implemented in Rensselaer's Voyager design space exploration system, for solving the scheduling problem in a 3dimensional (3D) design space: the usual 2D design space (which trades off area and schedule length), plus a third dimension representing clock length. Unlike design space exploration methodologies which rely on bounds or estimates, this methodology is guaranteed to find the globally optimal solution to a 3D scheduling problem. Furthermore, this methodology efficiently prunes the search space, eliminating provably inferior design points through: (1) a careful selection of candidate clock lengths, and (2) tight bounds on the number of functional units or on the schedule length. Both chaining and multicycle operations are supported. I. Introduction Highlevel synthesis is the design task of converting a behavioral description of a digital system into a registertransfer level design that implements that behavior. One of the cen...
An Exact Methodology for Scheduling in a 3D Design Space
 In Proceedings of the 1995 Interational Symposium on System Level Synthesis
, 1995
"... This paper describes an exact solution methodology, implemented in Rensselaer's Voyager design space exploration system, for solving the scheduling problem in a 3dimensional (3D) design space: the usual 2D design space (which trades off area and schedule length), plus a third dimension represen ..."
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Cited by 17 (2 self)
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This paper describes an exact solution methodology, implemented in Rensselaer's Voyager design space exploration system, for solving the scheduling problem in a 3dimensional (3D) design space: the usual 2D design space (which trades off area and schedule length), plus a third dimension representing clock length. Unlike design space exploration methodologies which rely on bounds or estimates, this methodology is guaranteed to find the globally optimal solution to the 3D scheduling problem. Furthermore, this methodology efficiently prunes the search space, eliminating provably inferior design points through: (1) a careful selection of candidate clock lengths, and (2) tight bounds on the number of functional units of each type or on the schedule length. 1 Introduction In highlevel synthesis, the process of solving the scheduling problem can be viewed as the process of exploring a 2dimensional (2D) design space, with axes representing time (schedule length) and area (ideally total area...
HighLevel Estimation Techniques for Usage in Hardware/Software CoDesign
 In IEEE/ACM Proc. of Asia and South Pacific Design Automation Conference
, 1998
"... Abstract Highlevel estimation techniques are of paramount importance for design decisions like hardwarekoftware partitioning or design space explorations. In both cases an appropriate compromise between accuracy and computation time determines about the feasibility of those estimation techniques. ..."
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Cited by 13 (1 self)
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Abstract Highlevel estimation techniques are of paramount importance for design decisions like hardwarekoftware partitioning or design space explorations. In both cases an appropriate compromise between accuracy and computation time determines about the feasibility of those estimation techniques. In this paper we present highlevel estimation techniques for hardware effort and hardwarekoftware communication time. Our techniques deliver fast results at sufficient accuracy. Furthermore, it is shown in which way these techniques are applied in order to cope with contradictory design goals like performance constraints and hardware effort constraints. As a solution, we present a cost function for the purpose of hardwarekoftware partitioning that offers a dynamic weighting of its components. The conducted experiments show that the usage of our estimation techniques in conjunction with their efficient combination leads to reasonable hardwarekoftware implementations as opposed to approaches that consider single constraints only. I.
A Unified Lower Bound Estimation Technique for HighLevel Synthesis
"... A Unified Lower Bound Estimation Technique for HighLevel Synthesis The importance of effective lower bound estimation (LBE) techniques is wellestablished in HighLevel Synthesis (HLS), since it allows more efficient exploration of the design space while providing other HLS tools with the capability ..."
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Cited by 11 (0 self)
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A Unified Lower Bound Estimation Technique for HighLevel Synthesis The importance of effective lower bound estimation (LBE) techniques is wellestablished in HighLevel Synthesis (HLS), since it allows more efficient exploration of the design space while providing other HLS tools with the capability of predicting the effect of specific tools on the design space. Much of previous work has focused on LBE techniques that use very simple cost models which primarily focus on the functional unit resources. With the push towards submicron technologies, simple models that use functional unit resources alone are not accurate enough to allow effective design space exploration since the effects of storage and interconnect can indeed dominate the cost function. In this paper, we present an integrated approach aimed at predicting lower bounds on hardware resources needed to implement a behavioral description within a given amount of time. Our area cost model accounts for storage (register) and int...
Fast SystemLevel AreaDelay Curve Prediction
 In Proc. of 1st APCHDLSA
, 1993
"... In this paper a unified approach of lower bound functional area and cycle budget estimations is presented to predict areadelay characteristics of designs at system level. The estimations are mainly based on relaxing precedence constraints in a behavioral design description and are the most accurat ..."
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Cited by 10 (3 self)
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In this paper a unified approach of lower bound functional area and cycle budget estimations is presented to predict areadelay characteristics of designs at system level. The estimations are mainly based on relaxing precedence constraints in a behavioral design description and are the most accurate estimations reported to date. 1. Introduction In highlevel synthesis, a data path consisting of modules (i.e. functional units), registers and interconnection units is synthesized from a behavioral design description [McFa90]. Such a description is represented by a data flow graph (DFG), which is a translation of an algorithmic specification in a hardware description language [Eijnd92]. The ability to predict the areadelay characteristics of designs without actually implementing them is important in producing quality designs in a reasonable time, and is therefore an important part of an (interactive) system design environment [Fleu93]. If a design will be part of a larger system, then...
A Comprehensive Estimation Technique for HighLevel Synthesis
, 1995
"... We present an integrated approach aimed at predicting layout area needed to implement a behavioral description for a given performance goal. Our approach is novel because: (1) it accounts for all types of RT level components (FUs, buses, registers), (2) it is highly flexible, allowing the designer t ..."
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Cited by 10 (0 self)
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We present an integrated approach aimed at predicting layout area needed to implement a behavioral description for a given performance goal. Our approach is novel because: (1) it accounts for all types of RT level components (FUs, buses, registers), (2) it is highly flexible, allowing the designer to tradeoff one type of resources with another, and considers dependencies between these different types, (3) it is vertically integrated to include provably accurate physical level estimators, and hence provides realistic accounting of layout effects, and (4) it uses a timing model with finer granularity, accounting for various delays in RTL datapaths. We demonstrate our technique on a variety of HLS benchmarks and show that efficient and effective design space exploration can be accomplished using this technique.
A quantitative prediction model for hardware/software partitioning
 in Proceedings of 17th International Conference on Field Programmable Logic and Applications (FPL07
, 2007
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Area Time Power Estimation for FPGA Based Designs at a Behavioral Level
, 2000
"... A new performance estimation technique for FPGA implementation based designs is presented. The interest and originality of the method is to rapidly test a great number of implementation solutions while staying independent as far as possible of the technology used, and to include power consumption es ..."
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Cited by 8 (1 self)
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A new performance estimation technique for FPGA implementation based designs is presented. The interest and originality of the method is to rapidly test a great number of implementation solutions while staying independent as far as possible of the technology used, and to include power consumption estimation. Thanks to this method, the designer can quickly have realistic information about the performances of a design, starting from a behavioral specification. 1.